Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification
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Summary of Contents for Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray
- Page 1 Intel® Xeon® Processor 5400 Series Specification Update December 2010 Document Number: 318585-019...
- Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548- 4725 or by visiting Intel's website at http://www.intel.com.
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Page 3: Table Of Contents
Content Revision History....................... 5 Preface ..........................6 Summary Tables of Changes..................8 Identification Information ....................15 Errata..........................18 Specification Changes....................41 Specification Clarifications ................... 42 Documentation Changes....................43 § Intel® Xeon® Processor 5400 Series Specification Update... - Page 4 Intel® Xeon® Processor 5400 Series Specification Update...
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Page 5: Revision History
No changes..released to keep in sync with other related -016 May 2009 documents. -017 Added Erratum AX73 June 2009 No changes..released to keep in sync with other related -018 December 2010 documents. -019 Added Erratum AX74-AX76 December 2010 Intel® Xeon® Processor 5400 Series Specification Update... -
Page 6: Preface
Processor Identification and the CPUID Instruction http://www.intel.com/ design/processor/ applnots/241618.htm Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M Intel® 64 and IA-32 Architectures Software Developer’s Manual, http://www.intel.com/... - Page 7 Nomenclature Errata are design defects or errors. These may cause the Intel® Xeon® Processor 5400 Series behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.
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Page 8: Summary Tables Of Changes
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® Xeon® Processor 5400 Series product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 9 Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology (Intel® HT Technology) on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
- Page 10 Intel® Core™ 2 Duo processor E8000 series AX = Intel® Xeon® Processor 5400 Series AY = Intel® Xeon® Processor 5200 Series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process AAA= Intel® Xeon® processor 3300 series AAB= Intel®...
- Page 11 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 2 AX24 No Fix May Terminate Early Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause AX25 No Fix an Unexpected Interrupt Intel® Xeon® Processor 5400 Series Specification Update...
- Page 12 RSM Instruction Execution under Certain Conditions May Cause Processor AX49 Fixed Hang or Unexpected Instruction Execution Results AX50 No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Intel® Xeon® Processor 5400 Series Specification Update...
- Page 13 Not-Present Page Faults May Set the RSVD Flag in the Error Code AX75 No Fix VM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction AX76 No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Intel® Xeon® Processor 5400 Series Specification Update...
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Page 14: Specification Changes
None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes Number DOCUMENTATION CHANGES None for this revision of this specification update. Intel® Xeon® Processor 5400 Series Specification Update... -
Page 15: Identification Information
Identification Information Component Identification via Programming Interface The Intel® Xeon® Processor 5400 Series stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number 31:28 27:20 19:16 15:14 13:12... - Page 16 Component Marking Information Intel® Xeon® Processor 5400 Series stepping can be identified by the following component markings: Figure 1. Processor Top-side Markings (Example) Legend: Mark Text (Production Mark ): 2.66GHz/12M/1333 GROUP1LINE1 GROUP1LINE1 Intel ® Xeon® GROUP1LINE2 GROUP1LINE2 SXXX XXXXX GROUP1LINE3 GROUP1LINE3 i (M) ©...
- Page 17 12 (2x6MB) Notes: Processors in the QDF/S-Spec column that begin with a Q are for qualification only. PPS Samples. E5405 does not support Intel SpeedStep® Technology. All others listed do support this technology. Intel® Xeon® Processor 5400 Series Specification Update...
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Page 18: Errata
Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault. - Page 19 Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Write Combining Memory Locations" will operate correctly.
- Page 20 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 21 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit.
- Page 22 Machine Check (#MC), etc.). If the RSM attempts to return to a non-canonical address, the address pushed onto the stack for this #GP fault may not match the non-canonical address that caused the fault. Intel® Xeon® Processor 5400 Series Specification Update...
- Page 23 Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 24 Implication: While in 64-bit mode, with count greater or equal to 2 , repeat string operations CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 2...
- Page 25 #MF. In this situation, the interrupt should be serviced before the #MF. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF may be serviced before higher priority interrupts.
- Page 26 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system. Workaround:...
- Page 27 Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 28 A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
- Page 29 Guest Interruptability-State Field Problem: As specified in Section, "VM Exits Induced by the TPR Shadow", in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the "use TPR shadow", "activate secondary controls", and "virtualize APIC accesses"...
- Page 30 VMCS. Such a VMM should be unaffected by this erratum. A VMM that does not emulate this behavior may need to recover the old value of RIP through alternative means. Intel has not observed this erratum with any commercially available software.
- Page 31 Implication: Under the scenario described above, the processor may hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. However, streaming behavior may be re-enabled by setting bit 5 to 1 of the MSR at address 0x21 for software development or testing purposes.
- Page 32 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 33 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
- Page 34 Implication: In general, VMM software that follows the guidelines given in the section “Handling VM Exits Due to Exceptions” of Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide should not be affected. If the erratum improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed by one instruction.
- Page 35 If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and the processor subsequently receives an INIT reset, the SYSCALL instructions will not behave as intended. Intel has not observed this erratum in any commercially available software.
- Page 36 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the far JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
- Page 37 The store operations done to save the processor context in the XSAVE instruction flow, when XSAVE is used to store only the SSE context, may appear to execute before the completion of older store operations. Intel® Xeon® Processor 5400 Series Specification Update...
- Page 38 Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may not follow program order and may execute before older stores. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 39 Implication: Software may erroneously infer that a page fault was due to a reserved-bit violation when it was actually due to an attempt to access a not-present page. Intel has not observed this erratum with any commercially available software. Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag is 0.
- Page 40 Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the ”Summary Tables of Changes”. Intel® Xeon® Processor 5400 Series Specification Update...
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Page 41: Specification Changes
Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5400 Series Datasheet There are no new Specification Changes in this Specification Update revision. Intel® Xeon® Processor 5400 Series Specification Update... -
Page 42: Specification Clarifications
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly. -
Page 43: Documentation Changes
All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. Note: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel®... - Page 44 Intel® Xeon® Processor 5400 Series Specification Update...