Intel F-Tile SDI II Agilex User Manual page 25

2. Design Example Detailed Description
710496 | 2022.01.28
Figure 19. Serial Loopback with Duplex Mode
Top
SDI Du Sys
2.3.2.1. Clocking Scheme Component
Table 10. Clocking Scheme Component
Diagram label
TX PLL refclock
Send Feedback
F-tile PMA/
F-tile PMA/
FEC Direct
FEC Direct
PHY IP (TX)
PHY IP (RX)
SDI F-tile
PHY Adapter
Reference
and System
PLL Clocks IP
RX CDR
Ref Clock
SysPLL
Ref Clock
TX PLL
Ref Clock
TX PLL reference clock which can be any clock frequency that is dividable by
transceiver for that data rate. This clock must be connected from a dedicated
transceiver reference clock pin to the input clock port of Reference and System
PLL Clocks IP, before connecting the corresponding output port to SDI top
module.
Du Top
SDI II
(Duplex)
TX PLL Refclock
System PLL Refclock
TX PLL/RX CDR Link Clock
TX/RX Transceiver Clkout
Description
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
Video Pattern
Generator
Pattern Gen
Control PIO
JTAG to Avalon
Master Bridge
Pattern Ctrl
Device_init
GPIO Clock
RX CDR Refclock
RX Coreclock
System PLL Output Link Clock
TX/RX Transceiver Clkout2
continued...
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