Intel F-Tile SDI II Agilex User Manual page 38

Table 22. Device Init module signals
Signal name
clk
init_done
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
38
Direction Width
Input 1
Output 1
2. Design Example Detailed Description
Description
Clock signal to reset delay module
Indicates device has finished its initialization stage after
a programmable delay which is determined by
parameter.
CNTR_BITS
Note: parameter determines the bit width of
CNTR_BITS
the delay counter. Default value is set to 16.
710496 | 2022.01.28
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