Intel F-Tile SDI II Agilex User Manual page 33

2. Design Example Detailed Description
710496 | 2022.01.28
Signal Name
sdi_tx_enable_crc
sdi_tx_enable_ln
sdi_tx_ln
sdi_tx_ln_b
sdi_tx_vpid_overwrit
e
sdi_tx_line_f0
sdi_tx_line_f1
sdi_tx_vpid_byte1
sdi_tx_vpid_byte2
sdi_tx_vpid_byte3
sdi_tx_vpid_byte4
sdi_tx_vpid_byte1_b
sdi_tx_vpid_byte2_b
sdi_tx_vpid_byte3_b
sdi_tx_vpid_byte4_b
sdi_tx_datavalid
sdi_rx_align_locked
sdi_rx_trs_locked
sdi_rx_clkout_is_nts
c_paln
sdi_rx_format
sdi_rx_ap
Send Feedback
Direction Width
Other SDI video protocol interfaces
Input 1
Input 1
Input 11*N
Input 11*N
Input 1
Input 11*N
Input 11*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Output 1
Output 1
Output N
Output 1
Output 4*N
Output N
F-Tile SDI II Intel
Description
• 3'b100: 6G-SDI 10-bit Multiplex Type 2
• 3'b111: 12G-SDI 10-bit Multiplex Type 1
• 3'b110: 12G-SDI 10-bit Multiplex Type 2
Enable CRC insertion for all SDI video standards except
SD-SDI.
Enable Line Number insertion for all SDI video standards
except SD-SDI.
Line number to be inserted in the data stream when
sdi_tx_enable_ln = 1.
Line number to be inserted in the data stream when
sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit
Multiplex Type 2.
Enable this signal to overwrite the existing payload ID
embedded in the data stream.
Indicates the line number to be inserted with Payload ID.
Payload ID byte to be inserted in the payload ID field.
Data valid signal generated from SDI TX core and has
the following timing synchronous to tx_vid_clkout:
• SD-SDI: 1H 4L 1H 5L
• HD-SDI: 1H 1L (for triple/multi rate)
• H (for single rate)
• 3G/6G/12G-SDI: H
Alignment locked indicating a TRS has been spotted and
word alignment performed.
TRS locked indicating six consecutive TRS with same
timing have been spotted.
Indicates that the receiver is receiving video rate at
integer or fractional frame rate.
• 0 – Integer frame rate
• 1 – Fractional frame rate
Received video transport format. Refer to IP User Guide
for the encoding value.
Active picture interval timing signal. This signal is
asserted when the active picture interval is active
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Agilex FPGA IP Design Example User Guide
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