Intel F-Tile SDI II Agilex User Manual page 23

2. Design Example Detailed Description
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Figure 17. Parallel Loopback with Duplex Mode
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SDI Du Sys
F-tile PMA/
F-tile PMA/
FEC Direct
FEC Direct
PHY IP (TX)
PHY IP (RX)
PHY Adapter
Reference
and System
PLL Clocks IP
RX CDR
Ref Clock
SysPLL
Ref Clock
TX PLL
Ref Clock
Du Top
SDI II
(Duplex)
SDI F-tile
TX PLL Refclock
System PLL Refclock
TX PLL/RX CDR Link Clock
TX/RX Transceiver Clkout
®
F-Tile SDI II Intel Agilex
Loopback Top
Loopback
FIFO
Device_init
GPIO Clock
RX CDR Refclock
RX Coreclock
System PLL Output Link Clock
TX/RX Transceiver Clkout2
™
FPGA IP Design Example User Guide
23