Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet
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Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

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®
Intel
Core™2 Extreme Processor
Δ
®
QX9000
Series, Intel
Core™2 Quad
Δ
Δ
Δ
Processor Q9000
, Q9000S
, Q8000
,
Δ
and Q8000S
Series
Datasheet
— on 45 nm process in the 775 land package
August 2009
Document Number: 318726-010

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Summary of Contents for Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor

  • Page 1 ® Intel Core™2 Extreme Processor Δ ® QX9000 Series, Intel Core™2 Quad Δ Δ Δ Processor Q9000 , Q9000S , Q8000 Δ and Q8000S Series Datasheet — on 45 nm process in the 775 land package August 2009 Document Number: 318726-010...
  • Page 2 Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.

  • Page 3: Table Of Contents

    Contents Introduction ......................11 Terminology ..................... 12 1.1.1 Processor Terminology Definitions ............12 References ....................... 14 Electrical Specifications ................... 15 Power and Ground Lands..................15 Decoupling Guidelines ..................15 2.2.1 VCC Decoupling ..................15 2.2.2 Vtt Decoupling ..................15 2.2.3 FSB Decoupling..................
  • Page 4 Sleep State ....................92 6.2.6 Deep Sleep State..................93 6.2.7 Deeper Sleep State .................93 ® 6.2.8 Enhanced Intel SpeedStep Technology ............94 Processor Power Status Indicator (PSI) Signal ............94 Boxed Processor Specifications................95 Introduction ......................95 Mechanical Specifications ..................96 7.2.1 Boxed Processor Cooling Solution Dimensions..........96 7.2.2...
  • Page 5 Processor Package Drawing (Sheet 1 of 3) .............. 36 Processor Package Drawing (Sheet 2 of 3) .............. 37 Processor Package Drawing (Sheet 3 of 3) .............. 38 ® Processor Top-Side Markings Example (Intel Core™2 Extreme Processor QX9650)..40 ® Processor Top-Side Markings Example (Intel Core™2 Quad Processor Q9000 Series) ..
  • Page 6 Package Handling Guidelines..................39 Processor Materials....................40 Alphabetical Land Assignments ................46 Numerical Land Assignment...................55 Signal Description ....................64 Processor Thermal Specifications ................76 ® Intel Core™2 Extreme Processor QX9770 Thermal Profile ........78 ® Intel Core™2 Extreme Processor QX9650 Thermal Profile ........79 ® Intel Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile.....80 ®...
  • Page 7 Q9400S, and Q8200S. ® -008 • Added Intel Core™2 Quad processors Q8400 and Q8400S April 2009 ® ® • Corrected list of Intel VT supported processors: Intel Core™2 Quad -009 May 2009 processors Q8400 and Q8400S ® -010 • Added Intel Core™2 Quad processors Q9505 and Q9505S...
  • Page 8 Datasheet...
  • Page 9 Intel architecture enables the processor to execute operating systems and applications written ® to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep technology, allows tradeoffs to be made between performance and power consumption. ® The Intel Core™2 Extreme processor QX9000 series, Intel Core™2 Quad processor Q9000, Q9000S,...
  • Page 10 TXT is a key element in Intel's safer computing initiative that defines a set of hardware enhancements that operate with an Intel TXT enabled operating system to help protect against software-based attacks. It creates a hardware foundation that builds on Intel's Virtualization Technology to help protect the confidentiality and integrity of data stored/created on the client PC.

  • Page 11: Introduction

    Q8400S. ® The processor is based on 45 nm process technology. The processor features the Intel Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces latency to frequently used data. The processors feature 1600 MHz and 1333 MHz front side bus (FSB) frequencies.The processors also feature two independent but shared...

  • Page 12: Terminology

    • Processor — For this document, the term processor is the generic form of the ® ® Intel Core™2 Extreme processor QX9000 series, the Intel Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series. ® ® • Enhanced Intel Core microarchitecture —...
  • Page 13 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Software Developer Guide at http:// developer.intel.com/technology/64bitextensions/.

  • Page 14: References

    Balanced Technology Extended (BTX) System Design Guide www.formfactors.org http://intel.com/design/ LGA775 Socket Mechanical Design Guide Pentium4/guides/ 302666.htm ® Intel 64 and IA-32 Intel Architecture Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M http://www.intel.com/ Volume 2B: Instruction Set Reference, N-Z products/processor/ manuals/...

  • Page 15: Electrical Specifications

    Electrical Specifications Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V , while all VSS lands must be connected to a system ground plane.

  • Page 16: Fsb Decoupling

    To support the Deeper Sleep State the platform must use a VRD 11.1 compliant solution. The Deeper Sleep State also requires additional platform support. For further information on Voltage Regulator-Down solutions, contact your Intel field representative. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings.

  • Page 17: Voltage Identification Definition

    Electrical Specifications Table 2-1. Voltage Identification Definition Voltage Voltage 1.0375 1.025 1.5875 1.0125 1.575 1.5625 0.9875 1.55 0.975 1.5375 0.9625 1.525 0.95 1.5125 0.9375 0.925 1.4875 0.9125 1.475 1.4625 0.8875 1.45 0.875 1.4375 0.8625 1.425 0.85 1.4125 0.8375 0.825 1.3875 0.8125 1.375 1.3625...

  • Page 18: Reserved, Unused, And Testhi Signals

    Electrical Specifications Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to V or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

  • Page 19: Voltage And Current Specification

    Electrical Specifications Voltage and Current Specification 2.6.1 Absolute Maximum and Minimum Ratings Table 2-2 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.

  • Page 20: Dc Voltage And Current Specification

    Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 2-3. Voltage and Current Specifications 2, 10 Symbol Parameter Unit Notes VID Range 0.8500 — 1.3625 Processor Number QX9770 3.20 GHz (12 MB Cache) Processor Number 775_VR_CONFIG_05B: QX9650 3.00 GHz (12 MB Cache) Processor Number 775_VR_CONFIG_05A: Q9650...

  • Page 21: Voltage And Current Specifications

    VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel ®...
  • Page 22 Electrical Specifications capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. Refer to Table 2-4 Figure 2-1 for the minimum, typical, and maximum V allowed for...
  • Page 23 Electrical Specifications Table 2-4. Static and Transient Tolerance 1, 2, 3, 4 Voltage Deviation from VID Setting (V) Maximum Voltage Typical Voltage Minimum Voltage 1.30 mΩ 1.38 mΩ 1.45 mΩ 0.000 -0.019 -0.038 -0.007 -0.026 -0.045 -0.013 -0.033 -0.053 -0.020 -0.040 -0.060 -0.026...

  • Page 24: Vcc Static And Transient Tolerance

    Electrical Specifications Figure 2-1. Static and Transient Tolerance Icc [A] VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.100 Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138...

  • Page 25: Vcc Overshoot

    Electrical Specifications 2.6.3 Overshoot The processor can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V is the maximum allowable overshoot voltage). OS_MAX OS_MAX The time duration of the overshoot event must not exceed T...

  • Page 26: Signaling Specifications

    GTLREF specifications). Termination resistors (R ) for GTL+ signals are provided on the processor silicon and are terminated to V . Intel chipsets will also provide on-die termination; thus, eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

  • Page 27: Signal Characteristics

    Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals Synchronous to GTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# BCLK[1:0] A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/ INTR, LINT1/NMI, SMI# , STPCLK#, PWRGOOD, SLP#, CMOS TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0], PSI# Open Drain FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M...

  • Page 28: Cmos And Open Drain Signals

    Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state.

  • Page 29: Platform Environment Control Interface (Peci) Dc Specifications

    2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These...

  • Page 30: Gtl+ Front Side Bus Specifications

    Electrical Specifications Table 2-12. PECI DC Electrical Limits Symbol Definition and Conditions Units Notes Input Voltage Range -0.15 Hysteresis 0.1 * V — hysteresis Negative-edge threshold voltage 0.275 * V 0.500 * V Positive-edge threshold voltage 0.550 * V 0.725 * V High level output source -6.0 source...

  • Page 31: Clock Specifications

    13.5 (see Table 2-14 for the processor supported ratios). The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency...

  • Page 32: Fsb Frequency Select Signals (Bsel[2:0])

    Q9000S, Q8000, and Q8000S series operate at a 1333 MHz FSB frequency (selected by ® a 333 MHz BCLK[1:0] frequency). The Intel Core™2 Extreme processor QX9770 operates at a 1600 MHz FSB frequency (selected by a 400 MHz BCLK[1:0] frequency) Individual processors will only operate at their specified FSB frequency.

  • Page 33: Fsb Differential Clock Specifications (1600 Mhz Fsb)

    Electrical Specifications Table 2-17. FSB Differential Clock Specifications (1600 MHz FSB) T# Parameter Unit Figure Notes BCLK[1:0] Frequency 397.962 400.037 T1: BCLK[1:0] Period 2.499766 2.512800 T2: BCLK[1:0] Period Stability 3, 4, 7 T5: BCLK[1:0] Rise and Fall Slew V/ns Rate Slew Rate Matching NOTES: Unless otherwise noted, all specifications in this table apply to all processor core...

  • Page 34: Differential Clock Waveform

    Electrical Specifications Figure 2-3. Differential Clock Waveform Overshoot BCLK1 Rising Edge Ringback Ringback Margin Threshold CROSS (ABS CROSS (ABS Region Falling Edge Ringback BCLK0 Undershoot Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T4: BCLK[1:0] pulse low time T5: BCLK[1:0] rise time through the threshold region T6: BCLK[1:0] fall time through the threshold region...

  • Page 35: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.

  • Page 36: Processor Package Drawing (Sheet 1 Of 3)

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 3) Datasheet...

  • Page 37: Processor Package Drawing (Sheet 2 Of 3)

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 3) Datasheet...

  • Page 38: Processor Package Drawing (Sheet 3 Of 3)

    Package Mechanical Specifications Figure 3-4. Processor Package Drawing (Sheet 3 of 3) Datasheet...

  • Page 39: Processor Component Keep-Out Zones

    Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate.

  • Page 40: Package Insertion Specifications

    Figure 3-5 Figure 3-6 show the topside markings on the processor. This diagram is to aid in the identification of the processor. ® Figure 3-5. Processor Top-Side Markings Example (Intel Core™2 Extreme Processor QX9650) INTEL ©'06 QX9650 INTEL® CORE™2 EXTREME SLAN3 XXXX 3.00GHZ/2M/1333/05B...
  • Page 41 Package Mechanical Specifications ® Figure 3-6. Processor Top-Side Markings Example (Intel Core™2 Quad Processor Q9000 Series) INTEL ©'06 Q9550 INTEL® CORE™2 Quad SLAN3 XXXX 2.83GHZ/2M/1333/05A [FPO](e4) ATPO Datasheet...

  • Page 42: Processor Land Coordinates And Quadrants, Top View

    Package Mechanical Specifications Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-7. Processor Land Coordinates and Quadrants, Top View Address/ Socket 775 Common Clock/ Quadrants Async Top View...

  • Page 43: Land Listing And Signal Descriptions

    Land Listing and Signal Descriptions Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown Figure 4-1 Figure 4-2.

  • Page 44: Land-Out Diagram (Top View - Left Side)

    Land Listing and Signal Descriptions Figure 4-1.land-out Diagram (Top View – Left Side) FC34 FC31 BSEL1 FC15 FC33 FC32 BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD D43# D41#...

  • Page 45: Land-Out Diagram (Top View - Right Side)

    Land Listing and Signal Descriptions Figure 4-2.land-out Diagram (Top View – Right Side) VID_SEL VSS_MB_ VCC_MB_ VSS_ VCC_ REGULATION REGULATION SENSE SENSE VID7 FC40 VID6 VID2 VID0 VID3 VID1 VID5 VRDSEL PROCHOT# FC25 VID4 ITP_CLK0 FC24 A35# A34# ITP_CLK1 BPM0# BPM1# A33# A32#...
  • Page 46 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Source Synch Input/Output BPMb0# Common Clock Input/Output Source Synch Input/Output BPMb1# Common Clock Input/Output Source Synch Input/Output...

  • Page 47: Alphabetical Land Assignments

    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type D32# Source Synch Input/Output DSTBP0# Source Synch Input/Output D33# Source Synch Input/Output DSTBP1# Source Synch Input/Output...

  • Page 48: Vcc

    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type PECI Power/Other Input/Output TESTHI5 Power/Other Input PROCHOT# Asynch CMOS Input/Output TESTHI6 Power/Other Input...
  • Page 49 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other AK12 Power/Other AG11 Power/Other AK14 Power/Other AG12 Power/Other AK15 Power/Other AG14...
  • Page 50 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type AN22 Power/Other Power/Other AN25 Power/Other Power/Other AN26 Power/Other Power/Other AN29 Power/Other Power/Other...
  • Page 51 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other AB23 Power/Other Power/Other AB24 Power/Other Power/Other AB25 Power/Other VCC_MB_ AB26 Power/Other...
  • Page 52 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type AG13 Power/Other AL13 Power/Other AG16 Power/Other AL16 Power/Other AG17 Power/Other AL17 Power/Other...
  • Page 53 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 54 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 55 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type VTT_OUT_RI AC28 Power/Other Power/Other Output AC29 Power/Other FC39 Power/Other AC30 Power/Other Power/Other Input A21#...
  • Page 56 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AE28 Power/Other AG14 Power/Other AE29 Power/Other AG15 Power/Other AE30 Power/Other AG16 Power/Other Output AG17...
  • Page 57 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AH30 Power/Other AK16 Power/Other BPM1# Common Clock Input/Output AK17 Power/Other BPM0# Common Clock Input/Output AK18 Power/Other...
  • Page 58 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type VID0 Asynch CMOS Output AN17 Power/Other VID2 Asynch CMOS Output AN18 Power/Other Power/Other AN19...

  • Page 59: Numerical Land Assignment

    Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D13# Source Synch Input/Output DBI3# Source Synch Input/Output COMP8 Power/Other Input D58# Source Synch Input/Output...
  • Page 60 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type RESERVED TESTHI2 Power/Other Input Power/Other TESTHI0 Power/Other Input D19# Source Synch Input/Output VTT_SEL Power/Other...
  • Page 61 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other FC32 Power/Other Power/Other FC33 Power/Other LINT0 Asynch CMOS Input...
  • Page 62 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other PWRGOOD Power/Other...
  • Page 63 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other FC0/ Power/Other BOOTSELECT...

  • Page 64: Alphabetical Signals Reference

    Land Listing and Signal Descriptions Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 10) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information.
  • Page 65 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 10) Name Type Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
  • Page 66 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64- bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
  • Page 67 FC0/BOOTSELECT is not used by the processor. When this land is FC0/ ® Other tied to V , previous processors based on the Intel NetBurst BOOTSELECT microarchitecture should be disabled and prevented from booting. FC signals are signals that are available for compatibility with Other other processors.
  • Page 68 When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is...
  • Page 69 FSB throughout the bus locked operation and ensure the atomicity of lock. On the processor these signals are not connected on the package (they are floating). As an alternative to MSID, Intel has MSID[1:0] Output implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor.
  • Page 70 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 10) Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
  • Page 71 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 10) Name Type Description SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant state, causes the processor to enter the Sleep state. In the Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
  • Page 72 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 9 of 10) Name Type Description In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
  • Page 73 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 10 of 10) Name Type Description The VID (Voltage ID) signals are used to support automatic selection of power supply voltages (V ). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply V the processor.
  • Page 74 Land Listing and Signal Descriptions Datasheet...

  • Page 75: Thermal Specifications And Design Considerations

    5.1.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T...

  • Page 76: Processor Thermal Specifications

    The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.

  • Page 77: Core™2 Extreme Processor Qx9770 Thermal Profile

    Thermal Specifications and Design Considerations ® Table 5-2. Intel Core™2 Extreme Processor QX9770 Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 37.8 42.2 46.6 51.1 38.1 42.5 46.9 51.3 38.3 42.7...

  • Page 78: Intel Core™2 Extreme Processor Qx9650 Thermal Profile

    Thermal Specifications and Design Considerations ® Table 5-3. Intel Core™2 Extreme Processor QX9650 Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 42.4 48.2 54.0 59.7 42.7 48.5 54.3 60.1 43.1 48.9...

  • Page 79: Core™2 Quad Processor Q9000 And Q8000 Series Thermal Profile

    Thermal Specifications and Design Considerations ® Table 5-4. Intel Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 44.8 52.1 59.4 66.6 45.4 52.6 59.9...

  • Page 80: Core™2 Quad Processor Q9000S And Q8000S Series Thermal Profile

    Thermal Specifications and Design Considerations ® Table 5-5. Intel Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 49.6 57.0 64.4 71.7 50.4 57.8 65.2...

  • Page 81: Thermal Metrology

    5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-5 illustrates where Intel recommends T thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2).
  • Page 82 Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.

  • Page 83: On-Demand Mode

    Thermal Specifications and Design Considerations Figure 5-6. Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.

  • Page 84: Prochot# Signal

    Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted.

  • Page 85: Platform Environment Control Interface (Peci)

    5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.

  • Page 86: Peci Specifications

    Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The PECI register resides at address 30h. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes.

  • Page 87: Features

    Features Features Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.

  • Page 88: Normal State

    LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more information.

  • Page 89: Extended Halt Powerdown State

    Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed...

  • Page 90: Extended Stop Grant State

    Features 6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled using BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state.

  • Page 91: Deep Sleep State

    Features state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state.

  • Page 92: Enhanced Intel Speedstep ® Technology

    Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology. This technology enables the processor to switch between frequency and voltage points, which may result in platform power savings. In order to support this technology, the system must support dynamic VID transitions.

  • Page 93: Boxed Processor Specifications

    Introduction The Intel Core™2 Extreme processor QX9650, Intel Core™2 quad-core processor Q9000, Q9000S, Q8000, and Q8000S series will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution.

  • Page 94: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.

  • Page 95: Boxed Processor Fan Heatsink Weight

    Boxed Processor Specifications Figure 7-4. Space Requirements for the Boxed Processor (overall view) 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2) for details on the processor weight and heatsink requirements.

  • Page 96: Boxed Processor Fan Heatsink Power Cable Connector Description

    Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 7-6 shows the location of the fan power connector relative to the processor socket.

  • Page 97: Thermal Specifications

    Boxed Processor Specifications Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.

  • Page 98: Variable Speed Fan

    Boxed Processor Specifications 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.

  • Page 99: Boxed Intel

    As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

  • Page 100: Boxed Intel ® Core™2 Extreme Processor Qx9650 Fan Heatsink Weight

    7.5.1 QX9650 Boxed Intel Core™2 Extreme Processor Fan Heatsink Weight ® The Boxed Intel Core™2 Extreme processor QX9650 fan heatsink weight will complies with the socket specifications. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2) for details on the processor weight and...

  • Page 101: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)

    Boxed Processor Specifications Figure 7-12. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) § Datasheet...
  • Page 102 Boxed Processor Specifications Datasheet...

  • Page 103: Debug Tools Specifications

    Debug Tools Specifications Debug Tools Specifications Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces ® ® (LAIs) for use in debugging Intel Core™2 Extreme processor QX9000 series, Intel Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series systems.
  • Page 104 Debug Tools Specifications Datasheet...

This manual is also suitable for:

Q9400s - core 2 quad 2.66ghz 6m l2 cache 1333mhz lga775 low power processorCore2 extreme qx9000 seriesCore2 quad q9000 seriesCore2 quad q9000s seriesCore2 quad q8000 seriesCore2 quad q8000s series

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