Clocking Scheme - Intel F-Tile SDI II Agilex User Manual

2.3.2. Clocking Scheme

Figure 16. Parallel Loopback with Simplex Mode
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SDI RX Sys
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
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Rx Top
F-tile PMA/
FEC Direct
SDI II
PHY IP (RX)
(RX)
SDI F-tile
PHY Adapter
TX PLL Refclock
System PLL Refclock
TX PLL/RX CDR Link Clock
TX/RX Transceiver Clkout
2. Design Example Detailed Description
Loopback Top
Loopback
FIFO
Device_init
GPIO Clock
RX CDR Refclock
RX Coreclock/DR Clocks
System PLL Output Link Clock
TX/RX Transceiver Clkout2
710496 | 2022.01.28
TX Top
SDI TX Sys
F-tile PMA/
FEC Direct
SDI II
PHY IP (TX)
(TX)
SDI F-tile
PHY Adapter
Reference
and System
PLL Clocks IP
RX CDR SysPLL TX PLL
Ref Clock Ref Clock Ref Clock
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