Intel F-Tile SDI II Agilex User Manual page 18

Figure 14. Serial Loopback with Simplex Mode
Top
TX Top
Note: Refer to
connections.
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
18
SDI TX Sys
F-tile PMA/
FEC Direct
SDI II
PHY IP (TX)
(TX)
SDI F-tile
PHY Adapter
Parallel Data
Serial Data
Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
2. Design Example Detailed Description
SDI RX Sys
F-tile PMA/
Video Pattern
FEC Direct
Generator
PHY IP (RX)
Pattern Gen
Control PIO
JTAG to Avalon
Master Bridge
Pattern Ctrl
Device_init
Control/Status
Avalon-MM
710496 | 2022.01.28
SDI II
(RX)
SDI F-tile
PHY Adapter
RX Top
Reference
and System
PLL Clocks IP
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