Intel F-Tile SDI II Agilex User Manual page 21

2. Design Example Detailed Description
710496 | 2022.01.28
Common Block
Device Initialization
Related Information
Intel Agilex Configuration User Guide
More information about Intel Agilex Reset Release IP.
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SDI mode
HD-SDI single rate
3G-SDI single rate
12G-SDI single rate
This module contains Reset Release Intel FPGA IP to provide a known initialized
state for system logic to begin operation. The module also includes a reset delay
block to further delay the signal status from the IP for a safer operation.
For more information, refer to Intel Agilex Reset Release Intel FPGA IP in Intel
Agilex Configuration User Guide.
F-Tile SDI II Intel
Description
Minimum System PLL output
frequency
150 MHz
300 MHz
600 MHz
® ™
Agilex FPGA IP Design Example User Guide
21