Intel F-Tile SDI II Agilex User Manual page 35

2. Design Example Detailed Description
710496 | 2022.01.28
Signal Name
tx_pll_locked
cdr_reconfig_busy
tx_reconfig_busy
Table 18. Loopback top signals
Signal Name
Clocks
sdi_tx_clkout
sdi_rx_clkout
sdi_rx_rst_proto
gxb_tx_ready
sdi_rx_dataout
sdi_rx_dataout_valid
sdi_rx_std
sdi_rx_trs
sdi_rx_trs_locked
sdi_rx_frame_locked
sdi_tx_dataout_valid
sdi_tx_datain
sdi_tx_datain_valid
sdi_tx_trs
sdi_tx_std
Note: N=4 for multi rate, otherwise N=1.
Send Feedback
Direction Width
Output 1
Output 1
Output 1
Direction Width
Input 1
Input 1
Resets
Input 1
Input 1
SDI related signals
Input 20*N
Input 1
Input 3
Input N
Input N
Input 1
Input 1
Output 20*N
Output 1
Output 1
Output 3
F-Tile SDI II Intel
Description
TX PLL lock status
RX CDR reconfiguration status
TX PLL / transceiver reconfiguration status
Description
TX transceiver recovered parallel clock for video data.
RX transceiver recovered parallel clock for video data.
Reset signal from RX SDI core to indicate that the
protocol is currently held in reset.
Used as a reset signal to internal FIFO to indicate that
the TX is ready to receive.
Receiver recovered parallel video data
Data valid signal generated from SDI RX core
Received video standard from SDI RX core
Receiver output signal from SDI core that indicates
current word is TRS.
TRS locked status signal from SDI RX core
Frame locked status signal from SDI RX core
Data valid signal generated from SDI TX core
Parallel video data input to SDI TX core.
Data valid for the transmitter parallel data to SDI TX
core.
Transmitter TRS input to indicate that the current word is
a TRS to SDI TX core.
Indicates the desired transmit video standard to SDI TX
core.
® ™
Agilex FPGA IP Design Example User Guide
35