Summary of Contents for Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor
Page 1
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet November 2006 Order Number: 315569, Revision: 001...
Page 2
The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Processor Materials.................... 44 Processor Markings.................... 45 Processor Land Coordinates ................45 Land Listing ....................... 49 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments ......49 4.1.1 Land Listing by Land Name ..............49 4.1.2 Land Listing by Land Number ..............60 Signal Definitions .......................
Page 4
Debug Tools Specifications ..................111 Debug Port System Requirements ..............111 Target System Implementation................111 9.2.1 System Implementation................. 111 Logic Analyzer Interface (LAI) ................111 9.3.1 Mechanical Considerations ..............112 9.3.2 Electrical Considerations ................ 112 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Revision History Document Revision Description Date Number 315569 -001 Initial Release November 2006 § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Page 8
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
64-bit extension technology. Further details on Intel 64 architecture and its programming model can be found in the Intel® 64 and IA-32 Architecture Software Developer's Manual. In addition, the Quad-Core Intel® Xeon® Processor 5300 Series supports the Execute Disable Bit functionality.
2.13.1). Refer to the appropriate platform design guidelines for implementation details. The Quad-Core Intel® Xeon® Processor 5300 Series support either 1333 or 1066 MHz Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol and Source-Synchronous Transfer (SST) of address and data to improve performance.
• Quad-Core Intel® Xeon® Processor 5300 Series – Intel 64-bit microprocessor intended for dual processor servers and workstations. The Quad-Core Intel® Xeon® Processor 5300 Series is based on Intel’s 65 nanometer process, in the FC-LGA6 package with four processor cores. For this document, “processor” is used as the generic term for the “Quad-Core Intel®...
Page 12
FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ.
– The processor core power supply. • V – The processor ground. • V – FSB termination voltage. (Note: In some Intel processor EMTS documents, is instead called V State of Data The data contained within this document is the most accurate information available by the publication date of this document.
Page 14
Introduction Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
V . The on-die termination resistors are always enabled on the processor to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals.
ESR bulk capacitors and high frequency ceramic capacitors. For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor. It is possible to override this setting using software (see the Intel® 64 and IA-32 Architectures Software Developer’s Manual). This permits operation at lower frequencies than the processor’s tested frequency.
Individual processors operate only at or below the frequency marked on the package. Listed frequencies are not necessarily committed production frequencies. For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. The lowest bus ratio supported is 1/6.
Table 2-3 is not related in any way to previous Intel® Xeon® processors or voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself.
When the “111111” VID pattern is observed, the voltage regulator output should be disabled. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5300 Series. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see Section 6.2.3), Extended HALT state transitions (see...
Dual-Core Intel® Xeon® Processor 5000 Series Dual-Core Intel® Xeon® Processor 5100 Series Reserved All Quad-Core Intel® Xeon® Processor 5300 Series Note: The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor. Table 2-5.
These signals may be driven simultaneously by multiple agents (Wired-OR). Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update.
REQ[4:0]#, RS[2:0]#, RSP#, TRDY# Note: Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. CMOS Asynchronous and Open Drain...
Figure 2-1. Input Device Hysteresis Maximum V PECI High Range Minimum V Minimum Valid Input Hysteresis Signal Range Maximum V Minimum V PECI Low Range PECI Ground Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
FSB frequency, core frequency, number of cores, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.
Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ.
Page 28
The processor is CC_MAX capable of drawing I for up to 10 ms. Refer to Figure 2-2 Figure 2-3 for further details on the CC_MAX average processor current draw over various time durations. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
1.2 V. 17. I is specified while PWRGOOD and RESET# are asserted. CC_RESET Figure 2-2. Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time 10 0 0 .0 1 0 . 1 10 0 10 0 0...
VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. value greater than 90 A is not applicable for the Quad-Core Intel® Xeon® Processor E5300 Series. Figure 2-4. Quad-Core Intel® Xeon® Processor E5300 Series V...
VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Table 2-17. V Overshoot Specifications Symbol Parameter Units Figure Notes Magnitude of V overshoot above VID OS_MAX Time duration of V overshoot above VID µs OS_MAX Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
GTLREF_ADD_END specifications. The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Note: Please refer to Table 2-15 for TAP Signal Group DC specifications for TAP Signal Group AC specifications. § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Mechanical Specifications Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5300 Series are packaged in a Flip Chip Land Grid Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The package consists of two processor dies mounted on a pinless substrate with 771 lands.
Processor Package Drawing (Sheet 1 of 3) Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
It is a relatively slow bending event compared to shock and vibration tests. For more information on the transient bend limits, please refer to the MAS document entitled Manufacturing with Intel® Components using 771-land LGA Package that Interfaces with the Motherboard via a LGA771 Socket.
LGA771 socket, which meets the criteria outlined in the LGA771 Socket Design Guidelines. Processor Mass Specifications The typical mass of the Quad-Core Intel® Xeon® Processor 5300 Series is 21.5 g (0.76 oz). This includes all components which make up the entire processor product. Processor Materials The Quad-Core Intel®...
Mechanical Specifications Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram aids in the identification of the Quad-Core Intel® Xeon® Processor 5300 Series. Figure 3-5. Processor Top-side Markings (Example) Legend: Mark Text (Production Mark): 2.66GHZ/8M/1333 GROUP1LINE1 GROUP1LINE1 Intel ®...
Mechanical Specifications Figure 3-6. Processor Land Coordinates, Top View Address / Socket 771 Common Clock / Quadrants Async Top View Data / Clocks Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must be connected to the appropriate pins on all Quad-Core Intel® Xeon® Processor 5300 Series FSB agents. ADSTB[1:0]#...
Page 72
COMP[3:0] COMP[3:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines for implementation details. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Page 73
DBR# is used by a debug port interposer so that an in-target probe can drive reset. If a debug port connector is implemented in the system, DBR# is a no- connect on the Quad-Core Intel® Xeon® Processor 5300 Series package. DBR# is not a processor signal.
Page 74
When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service.
Page 75
The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. These signals are not connected to the processor die. A logic 0 is pulled to ground and a logic 1 is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series package.
Page 76
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Page 77
TRST# TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. The Quad-Core Intel® Xeon® Processor 5300 Series implement an on-die PLL filter CCPLL solution. The V input is used as a PLL supply voltage.
Page 78
Notes: For this processor land on the Quad-Core Intel® Xeon® Processor 5300 Series, the maximum number of symmetric agents is one. Maximum number of priority agents is zero. For this processor land on the Quad-Core Intel® Xeon® Processor 5300 Series, the maximum number of symmetric agents is two.
Thermal Specifications Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5300 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
It should be noted that the upper point associated with the CASE Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile B (x = TDP and y = @ TDP) represents a thermal solution design point. In actuality the CASE_MAX_B...
Please refer to Table 6-2 for discrete points that constitute the thermal profile. Refer to the Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. Table 6-2. Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile Table Power (W) (°C)
Implementation of Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet processor Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss. (See Section 6.2...
6.2.1 Thermal Monitor Features Quad-Core Intel® Xeon® Processor 5300 Series provide two thermal monitor features, Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled, TM2 will be activated first and TM1 will be added if TM2 is not effective.
The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the Quad-Core Intel® Xeon® Processor 5300 Series). When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs rapidly, on the order of 5 µs.
Demand” mode and is distinct from the Thermal Monitor 1 and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems utilizing the Quad-Core Intel® Xeon® Processor 5300 Series must not rely on software usage of this mechanism to limit the processor temperature.
TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architecture Software Developer’s Manual for specific register and programming details.
PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and must be enabled through BIOS. More information on this can be found in the Intel® 64 and IA-32 Architecture Software Developer’s Manual.
PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other compatible industry standard interfaces. The PECI client is as reliable as the device that it is embedded within, and thus given operating conditions Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Table 6-6 below: Table 6-6. GetTemp0() and GetTemp1() Error Codes Error Code Description 0x8000 General sensor error Sensor is operational, but has detected a temperature below its operational range 0x8002 (underflow). § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Address lands not identified in this table as configuration options should not be asserted during RESET#. Requires de-assertion of PWRGOOD. Disabling of any of the cores within the Quad-Core Intel® Xeon® Processor 5300 Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).
7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. Refer to the Intel® 64 and IA-32 Architecture Software Developer’s Manual. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform.
Snoop State BCLK running Service snoops to caches Snoop Event Occurs Stop Grant State Stop Grant Snoop State BCLK running BCLK running Snoop Event Serviced Snoops and interrupts allowed Service snoops to caches Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. The Quad-Core Intel® Xeon® Processor 5300 Series will issue two Stop Grant Acknowledge special bus cycles, once for each die. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state.
Not all Quad-Core Intel® Xeon® Processor 5300 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update when available.
Page 96
Features Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Boxed Processor Specifications Boxed Processor Specifications Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Quad-Core Intel® Xeon® Processor 5300 Series will be offered as an Intel boxed processor. Intel will offer the Quad-Core Intel® Xeon® Processor 5300 Series boxed processor with two heat sink configurations available for each processor frequency: 1U passive/ 3U+ active combination solution and a 2U passive only solution.
Figure 8-4 through Figure 8-8. Figure 8-9 through Figure 8-10 are the mechanical drawings for the 4-pin board fan header and 4-pin connector used for the active CEK fan heat sink solution. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
3-wire designs. When operating in thermistor controlled mode, fan RPM is automatically varied based on the TINLET temperature measured by a thermistor located at the fan inlet of the heat sink solution. Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
5°C with an external ambient temperature RISE ° of 35 C. Following these guidelines will allow the designer to meet Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile and conform to the thermal requirements of the processor. 8.3.2.2...
Page 110
They are as follows: • CEK Spring (supplied by baseboard vendors) • Heat sink standoffs (supplied by chassis vendors) § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a Quad-Core Intel® Xeon® Processor 5300 Series based system that can make use of an LAI: mechanical and electrical.
Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide. § Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Need help?
Do you have a question about the E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor and is the answer not in the manual?
Questions and answers