Intel F-Tile SDI II Agilex User Manual page 24

Figure 18. Serial Loopback with Simplex Mode
Top
TX Top
F-tile PMA/
FEC Direct
PHY IP (TX)
Note:
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
24
SDI TX Sys
SDI II
(TX)
SDI F-tile
PHY Adapter
GPIO Clock
TX PLL Refclock
System PLL Refclock
TX PLL/RX CDR Link Clock
TX/RX Transceiver Clkout
2. Design Example Detailed Description
RX Top
F-tile PMA/
Video Pattern
FEC Direct
Generator
PHY IP (RX)
Pattern Gen
Control PIO
JTAG to Avalon
Master Bridge
Pattern Ctrl
Device_init
RX CDR Refclock
RX Coreclock
System PLL Output Link Clock
TX/RX Transceiver Clkout2
710496 | 2022.01.28
SDI RX Sys
SDI II
(RX)
SDI F-tile
PHY Adapter
Reference
and System
PLL Clocks IP
TX PLL SysPLL
Ref Clock Ref Clock
Send Feedback
RX CDR
Ref Clock