Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Specification
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Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Specification

Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Specification

Xeon processor 3300 series specification update, on 45 nm process in the 775-land lga package
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Intel® Xeon® Processor 3300
Series
Specification Update
- on 45 nm Process in the 775-land LGA Package
January 2012
Reference Number: 309007-011

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Summary of Contents for Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor

  • Page 1 Intel® Xeon® Processor 3300 Series Specification Update - on 45 nm Process in the 775-land LGA Package January 2012 Reference Number: 309007-011...
  • Page 2 BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http:// www.intel.com/technology/security...

  • Page 3: Table Of Contents

    Revision History ......................... 5 Preface ..........................6 Summary Tables of Changes..................... 8 Identification Information ....................14 Component Identification Information................15 Errata..........................17 Specification Changes...................... 40 Specification Clarifications ....................41 Documentation Changes....................42 Intel® Xeon® Processor 3300 Series Specifcation Update January 2012...
  • Page 4 Intel® Xeon® Processor 3300 Series Specifcation Update January 2012...

  • Page 5: Revision History

    Updated Component Identification section with L3360 processor info February 2009 -009 Updated Component Identification section with X3380 processor info March 2, 2009 -010 Updated Erratum AAA1 March 11, 2009 Added Erratum AAA76 -011 January 2012 Added Erratum AAA77 Intel® Xeon® Processor 3300 Series Specification Update January 2012...

  • Page 6: Preface

    Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications. Intel® Xeon® Processor 3300 Series Specification Update January 2012...
  • Page 7 Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). Intel® Xeon® Processor 3300 Series Specification Update January 2012...

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 10 AT = Intel® Celeron® processor 200 series AV = Intel® Core™ 2 Extreme Processor QX9650 Intel® Core™ 2 Extreme Processor QX9650 and Intel® Core™ 2 Quad Processor Q9000 Series AW = Intel® Core™ 2 Duo desktop processor E8000 and E7000 series AX = Intel®...
  • Page 11 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field Using Memory Type Aliasing with cacheable and WC Memory Types AAA42 No Fix May Lead to Memory Ordering Violations Intel® Xeon® Processor 3300 Series Specification Update January 2012...
  • Page 12 XRSTORE Instruction May Cause Extra Memory Reads AAA67 Plan Fix CPUID Instruction May Return Incorrect Brand String Global Instruction TLB Entries May Not be Invalidated on a VM Exit or AAA68 No Fix VM Entry Intel® Xeon® Processor 3300 Series Specification Update January 2012...
  • Page 13 Table 1. Errata (Sheet 4 of 4) Plan ERRATA When Intel® Deep Power-Down State is Being Used, AAA69 No Fix IA32_FIXED_CTR2 May Return Incorrect Cycle Counts Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May AAA70 No Fix...

  • Page 14: Identification Information

    Identification Information Figure 1. Processor Package Example INTEL ©'06 3300 INTEL® XEON® SLxxx [COO] 2.83GHZ/2M/1333/05 [FPO] ATPO S/ N Intel® Xeon® Processor 3300 Series Specification Update January 2012...

  • Page 15: Component Identification Information

    Component Identification Information The Intel® Xeon® Processor 3300 Series can be identified by the following values: Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number 31:28 27:20 19:16 15:14 13:12 11:8 00000000b 0001b 0110b 0111b XXXXb When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
  • Page 16 Table 2. Intel® Xeon® Processor 3300 Series Identification Information L2 Cache Core Processor Processor Speed Core/ S-Spec Size Package Notes Stepping Signature Number (bytes) 12 MB 2.83 GHz / 1, 2, 3, 4, 5, 6, 7, 8, SLAN5 10676h X3360...

  • Page 17: Errata

    Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault.
  • Page 18 Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section “Buffering of Write Combining Memory Locations” will operate correctly.
  • Page 19 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 20 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit.
  • Page 21 Machine Check (#MC), and so forth). Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Intel® Xeon® Processor 3300 Series Specification Update January 2012...
  • Page 22 Store Ordering May be Incorrect between WC and WP Memory Types Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do.
  • Page 23 Implication: While in 64-bit mode, with count greater or equal to 2 , repeat string operations CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 2 Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 24 #MF. In this situation, the interrupt should be serviced before the #MF. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending #MF may be serviced before higher priority interrupts.
  • Page 25 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system. Workaround:...
  • Page 26 Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 27 A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 28 Guest Interruptibility-State Field Problem: As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR shadow", "activate secondary controls”, and “virtualize APIC accesses”...
  • Page 29 VMCS. Such a VMM should be unaffected by this erratum. A VMM that does not emulate this behavior may need to recover the old value of RIP through alternative means. Intel has not observed this erratum with any commercially available software.
  • Page 30 Implication: Under the scenario described above, the processor may hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. However, streaming behavior may be re-enabled by setting bit 5 to 1 of the MSR at address 0x21 for software development or testing purposes.
  • Page 31 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 32 Workaround: As recommended in the IA32 Intel® Architecture Software Developer’s Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum.
  • Page 33 Implication: In general, VMM software that follows the guidelines given in the section “Handling VM Exits Due to Exceptions” of Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide should not be affected. If the erratum improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed by one instruction.
  • Page 34 VMCS, VM entry may fail as described in Section “VM-Entry Failures ® During or After Loading Guest State” of Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.) Note that the...
  • Page 35 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode” recommends the far JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
  • Page 36 Status: For the steppings affected, see the Summary Tables of Changes. AAA69. When Intel® Deep Power-Down State is Being Used, IA32_FIXED_CTR2 May Return Incorrect Cycle Counts Problem: When the processor is operating at an N/2 core to front side bus ratio, after exiting Deep Power-Down State, the internal increment value for IA32_FIXED_CTR2 (Fixed Function Performance Counter 2, 30BH) will not take into account the half ratio setting.
  • Page 37 If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and the processor subsequently receives an INIT reset, the SYSCALL instructions will not behave as intended. Intel has not observed this erratum in any commercially available software.
  • Page 38 Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may not follow program order and may execute before older stores. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 39 Implication: Due to this erratum, SINIT ACM Q45_Q43_SINIT_19.BIN and earlier will be revoked. Workaround: It is possible for the BIOS to contain a workaround for this erratum. All Intel® TXT enabled software must use SINIT ACM Q45_Q43_SINIT_51.BIN or later. Status: For the steppings affected, see the Summary Tables of Changes.

  • Page 40: Specification Changes

    • Intel 64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate processor documentation. § Intel® Xeon® Processor 3300 Series Specification Update January 2012...

  • Page 41: Specification Clarifications

    Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

  • Page 42: Documentation Changes

    64 and IA-32 Architectures Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel and IA-32 Architectures Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.

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