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1. F-Tile SDI II Intel
Agilex
710496 | 2022.01.28
Table 3.
Jumper Settings and Descriptions
Jumper Block
J7
J8
J9
Related Information
Agilex I-series SoC Development Kit User Guide
1.5. Design Example Parameters
Table 4.
Parameters available in Design Example tab
Parameter
Select Design
Simulation
Synthesis
Generate File Format
Select Daughter card
Select Board
Send Feedback
™
FPGA IP Design Example Quick Start Guide
Description
Programming Header
To switch the generated clock
frequency to TX channel:
•
Pin 1-2 = 297 Mhz
•
Pin 2-3 = 297/1.001 Mhz
To select SDI or IP mode:
•
Pin 1-2 = SDI mode
•
Pin 2-3 = IP mode
Value
•
Parallel loopback with
external VCXO
•
Serial loopback
On / Off
On
•
Verilog
•
VHDL
•
Nextera VIDIO 12G-SDI
FMC card
•
No Development Kit
•
Agilex I-Series SOC
Development Kit
•
Custom Development Kit
-
1-2: 297 Mhz
2-3: 297/1.001 Mhz
1-2
Description
Select available design example to be generated.
•
Parallel loopback with external VCXO: Parallel
loopback design with an external VCXO to synchronize
the clock between RX and TX.
•
Serial loopback: An internal video pattern generator
generates along with TX and transmits to RX. This
design allows simple demonstration when you do not
have a video source available.
Turns on this option to generate necessary files for
simulation testbench.
Turns on this option to generate necessary files forIntel
Quartus Prime compilation and hardware demo.
This option is greyed out and set to always Enabled. This is
because synthesis files are still required to run Support-
Logic Generation stage in Intel Quartus Prime to generate
the transceiver tile's files which are essential to run
simulation as well.
Select the HDL format for generated design example fileset.
Note that the HDL format only affects the generated top
level IP files. All the other files, for example testbenches
and top level files for hardware demo are in Verilog.
Select the daughter card for the targeted design example.
This option is greyed out as only Nextera VIDIO 12G-SDI
FMC card is supported in this design example.
Select the board for the targeted design example.
®
™
F-Tile SDI II Intel
Agilex
FPGA IP Design Example User Guide
Setting
continued...
11
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