Intel F-Tile SDI II Agilex User Manual page 5

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1. F-Tile SDI II Intel Agilex
710496 | 2022.01.28
Folders
tx
phy_adapter
Table 2. Other Generated Files in Simulation Folder
Folders
mentor
synopsys
testbench
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FPGA IP Design Example Quick Start Guide
<qsys generated folder>
/tx_<vid_std>_top.sv
/sdi_<vid_std>_tx_sys.qsys
<qsys generated folder>
/sdi_ftile_phy_adapter.sv
/sdi_ftile_phy_adapter.sdc
/rxdata_dcfifo.ip
/rxdata_mwfifo.ip
[Only in 12-SDI single rate mode Design Example]
txdata_fifo.ip
<ip generated folder>
/mentor.do
/vcs/filelist.f
/vcs/vcs_sim.sh
/vcsmx/vcsmx_sim.sh
tb_top.sv
rx_checker/sdi_ii_tb_rx_checker.v
rx_checker/tb_data_compare.v
rx_checker/tb_dual_link_sync.v
rx_checker/tb_fifo_line_test.v
rx_checker/tb_frame_locked_test.sv
rx_checker/tb_ln_check.v
rx_checker/tb_rxsample_test.v
rx_checker/tb_trs_locked_test.sv
rx_checker/tb_txpll_test.sv
rx_checker/tb_vpid_check.v
tb_control/sdi_ii_tb_control.v
tb_control/tb_clk_rst.v
tb_control/tb_data_delay.v
tb_control/tb_serial_delay.sv
tb_control/tb_tasks.v
tb_checker/sdi_ii_tb_tx_checker.v
Files
(optional)
Files
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F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
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