Intel F-Tile SDI II Agilex User Manual page 4

Figure 2. Directory Structure for the Design Examples
quartus
sdi_ii_agi_demo.qpf
sdi_ii_agi_demo.qsf
Table 1. Other Generated Files in RTL Folder
Folders
vid_pattgen
loopback
du
rx
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
4
1. F-Tile SDI II Intel
hwtest
(for serial loopback design)
qdb
tpg.ctrl.tcl
/sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/pattgen_ctrl.qsys
<qsys generated folder>
/loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/du_<vid_std>_top.v
sdi_<vid_std>_du_sys.qsys
<qsys generated folder>
/rx_<vid_std>_top.v
/sdi_<vid_std>_rx_sys.qsys
® ™
Agilex FPGA IP Design Example Quick Start Guide
<Design Example>
simulation
rtl
sdi_ii_agi_demo.sv
mentor
sdi_ii_agi_demo.sdc
synopsys
edge_detector.sv
testbench
clock_heartbeat.v
xcelium
sgpio_slave.v
alt_reset_delay.v
sim_setup_gen.sh
device_init.sv
jtag.sdc
reset_release.ip
xcvr_ref_sysclk.ip
<reset_release ip generated folder >
<xcvr_ref_sysclk ip generated folder>
vid_pattgen (for serial loopback design)
loopback (for parallel loopback design)
du (for duplex mode design)
rx (for simplex mode design)
tx (for simplex mode design)
phy_adapter
Files
(optional)
710496 | 2022.01.28
generation.log
continued...
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