Pld Test Register 2; Pld Gpio2 Interrupt Register; Table 5-16 Pld Test Register 2; Table 5-17 Pld Gpio2 Interrupt Register - SMART Embedded Computing MVME2500 Installation & Use Manual

5.5.13

PLD Test Register 2

The MVME2500 PLD provides an 8-bit general purpose read/write register which is used
by the software for PLD testing or general status bit storage.

Table 5-16 PLD Test Register 2

REG
Bit
Field
OPER
RESET
Field Description
TEST_REG2
5.5.14

PLD GPIO2 Interrupt Register

The Abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2500
provides an interrupt register that the system software reads to determine which device the
interrupt originated from. GPIO2 will be driven Low if any of the interrupts asserts.

Table 5-17 PLD GPIO2 Interrupt Register

REG
Bit
Field
OPER
RESET 0
Field Description
NMI
TICK0_INT
MVME2500 Installation and Use (6806800L01S)
PLD Test Register 2- 0xFFDF0081
7 6 5
TEST_REG2
R/W
00
General purpose 8-bit R/W field
PLD Write Protect I2C Debug- 0xFFDF0095
7 6 5
RSVD RSVD RSVD
R
0 0
Abort switch interrupt if pressed less than three seconds.
1 - Interrupt enabled
0 - No Interrupt
Tick Timer 0 interrupt
1 - Interrupt enabled
0 - No Interrupt
Memory Maps and Registers
4 3
4 3 2
RSVD NMI TICK0_INT
0 0 0
2 1 0
1 0
TICK1_INT TICK2_INT
0 0
99