Pld Watchdog Timer Refresh Register; Table 5-19 Pld Watchdog Timer Refresh Register - SMART Embedded Computing MVME2500 Installation & Use Manual

CPU_RESET
WD_TIMEOUT
LRSTO
Sft_RST
5.5.16

PLD Watchdog Timer Refresh Register

The MVME2500 provides a watchdog timer refresh register.

Table 5-19 PLD Watchdog Timer Refresh Register

REG PLD Watch Dog Timer Load - 0xFFC80600
Bit 15
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Refresh
OPER R
RESET 0000
Field Description
Refresh
MVME2500 Installation and Use (6806800L01S)
CPU_HRESET_REQ_L Reset Reason
1 - Reset is due to CPU_HRESET_REQ_L signal
0 -None
Watchdog Timeout Reset Reason
1 - Reset is due to watchdog timing out
0 - None
TSI LRSTO Reset Reason
1 - Reset is due to LRSTO signal
0 - None
Soft Reset - Reset Reason
1 - Reset is due to Soft_RST register being set, or the front
panel switch being pressed more than three
0 - None
14 13 12
Counter Refresh. When the pattern 0x00DB is written, the watchdog counter will be
reset to zero.
Memory Maps and Registers
11 10 9 8 7 6 5 4 3 2 1 0
101