System Clock; Real Time Clock Input; Local Bus Controller Clock Divisor; Table 7-7 System Clock - SMART Embedded Computing MVME2500 Installation & Use Manual

Programming Model
Table 7-6
Device
TSI148
RTC
FPGA
QUART
ICS83905
7.7.1

System Clock

The system and DDR clock is driven by ICS840S07I device. The following table defines the
clock frequency.
Table 7-7
SYSCLK
100MHz
7.7.2

Real Time Clock Input

The RTC clock input is driven by a 1MHz clock generated by the FPGA. This provides a
fixed clock reference for the QorIQ P20x0 PIC timers which the software can use as a
known time reference.
7.7.3

Local Bus Controller Clock Divisor

The local bus controller (LBC) clock output is connected to the FPGA for LBC bus
transaction. It is also the source of 1 MHz (CPU_RTC) and FPGA tick timers.
126
Clock Distribution (continued)
Clock Signal
CLK_PCI_BR3
CLK_32K
CPU_LCK0
CLK_QUART
CLK_25MHZ_ICS9FG108
System Clock
CORE
800/1200MHz
Frequency
133MHz
32.768KHz
25MHz
1.8432MHz
25MHz
CCB Clock (Platform)
400MHz
MVME2500 Installation and Use (6806800L01S)
Programming Model
Clock Tree
VIO
Source
ICS840S07I +3.3V
DS32KHz +3.3V
QorIQ P20x0 +3.3V
FPGA +3.3V
ICS83905AGILF +3.3V
DDR3 LBC
400MHz 25MHz