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SMART Embedded Computing MVME6100 Programmer's Reference Manual

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MVME6100 Single Board Computer
Programmer's Reference
P/N: 6806800J39C
September 2019

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Summary of Contents for SMART Embedded Computing MVME6100

  • Page 1 MVME6100 Single Board Computer Programmer’s Reference P/N: 6806800J39C September 2019...
  • Page 2 Computing” and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners. These materials are provided by SMART Embedded Computing as a service to its customers and may be used for informational purposes only. Disclaimer* SMART Embedded Computing (SMART EC) assumes no responsibility for errors or omissions in these materials.

  • Page 3: Table Of Contents

    2.1.12.2 PCI Configuration Space ........39 MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 4 Related Documentation ............45 A.1 SMART Embedded Computing Documentation ....... . . 45 A.2 Manufacturers’...

  • Page 5: List Of Figures

    MVME6100 Board Layout Diagram ........
  • Page 6 Table of Contents MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 7: List Of Tables

    MVME6100 Features Summary ........
  • Page 8 Table of Contents MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 9: About This Manual

    The MVME6100 Single Board Computer Programmer’s Reference Guide provides general programming information, including memory maps, interrupts, and register data for the MVME6100 family of boards. This document should be used by anyone who wants general, as well as technical information about the MVME6100 products.
  • Page 10 Used for on-screen output and code related elements or commands. Screen Sample of Programming used in a table (9pt) Courier + Bold Used to characterize user input and to separate it from system output MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 11 Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message Indicates a hot surface that could result in moderate or serious injury Indicates an electrical situation that could result in moderate injury or death MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 12: Summary Of Changes

    Computing template. Updated Conventions table. Removed ordering table; added Ordering and Support Information. 6806800J39B May 2014 Updated table MVME6100 Features Summary on page 13. Re-branded to Artesyn template. 6806800J39A July 2009 Initial Version MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 13: Introduction

    Introduction Features This chapter briefly describes the board level hardware features of the MVME6100 single board computer, including a table of features and a block diagram. The remainder of the chapter provides memory map information including a default memory map, MOTLoad’s processor memory map, a default PCI memory map, MOTLoad’s PCI memory map, a PCI...
  • Page 14 Supports 33/66 MHz, 32/64-bit PCI bus  Access through PCI6520 bridge to PMCspan Form Factor Standard 6U VME  Combined reset and abort switch  Status LEDs Miscellaneous  8-bit software-readable switch  VME geographical address switch MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 15 Introduction Figure 1-1 MVME6100 Board Layout Diagram MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 16: Memory Maps

    PCI Bus 0 Memory Space 0 1400 0000 1BFF FFFF 128M Unassigned 1C00 0000 1C7F FFFF Device CS0* 1C80 0000 1CFF FFFF Device CS1* 1D00 0000 1DFF FFFF Device CS2* 1E00 0000 1FFF FFFF Unassigned MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 17 PCI Bus 0 Memory Space 3 F800 0000 FEFF FFFF 112M Unassigned FF00 0000 FF7F FFFF Device CS3* Boot Flash (Bank A or B depending FC00 0000 FFFF FFFF on S4:3 switch setting) Set by configuration resistors. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 18: Motload's Processor Memory Map

    F400 0000 F7FF FFFF Device CS0* Flash Bank A F800 0000 FBFF FFFF Device Boot Flash Bank B The internal registers only occupy the first 64KB, but minimum address decoding resolution is 1MB. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 19: Default Pci Memory Map

    2800M Unassigned F200 0000 F3FF FFFF PCI Bus 1 P2P Memory Space 1 F400 0000 FEFF FFFF 176M Unassigned FF00 0000 FF7F FFFF Device CS3* FC00 0000 FFFF FFFF Boot Flash Bank B MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 20: Motload's Pci Memory Maps

    System Memory (on-board DRAM) 1.2.5 VME Memory Map The MVME6100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2GB. 1.2.6 System I/O Memory Map System resources including system control and status registers, NVRAM/RTC, and the 16550 UART are mapped into a 1MB address range assigned to Device Bank 1.

  • Page 21: System Status Register 1

    Introduction 1.2.6.1 System Status Register 1 The MVME6100 board System Status Register 1 is a read-only register used to provide board status information. Table 1-7 System Status Register 1 System Status Register 1- 0xF1100000 FIELD OPER RESET REF_CLK Reference clock. This bit reflects the current state of the 28.8 KHz reference clock derived from the 1.8432 MHz UART oscillator divided by 64.

  • Page 22: System Status Register 2

    MV64360 was initialized using the MV64360 User Defined Initialization SROM at $A6. 1.2.6.2 System Status Register 2 The MVME6100 board system status register 2 provides board control and status bits. Table 1-8 System Status Register 2 System Status Register 2- 0xF1100001...

  • Page 23: System Status Register 3

    OPER RESET BOARD_RESET Board Reset. Setting this bit will force a hard reset of the MVME6100 board. This bit will clear automatically when the board reset is complete. This bit will always be cleared during a read. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 24: Presence Detect Register

    PMC Module 0 Present. If set, there is no PMC module installed in slot 0. If cleared, the PMC module is installed. PMC1P_L PMC Module 1 Present. If set, there is no PMC module installed in slot 1. If cleared, the PMC module is installed. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 25: Configuration Header/Switch Register (S1)

    Introduction 1.2.6.5 Configuration Header/Switch Register (S1) The MVME6100 board has an 8-bit header or switch that may be read by the software. Table 1-11 Configuration Header/Switch Register Configuration Header/Switch Register - 0xF1100005 FIELD OPER RESET CFG[7-0] Configuration Bits 7-0. These bits reflect the position of the switch installed in the configuration header location.

  • Page 26: Time Base Enable Register

    MV64360 device controller bus to provide asynchronous debug ports. The Quad UART supports up to four asynchronous serial ports of which two are used on the MVME6100. The ST16C554D is a universal asynchronous receiver and transmitter and is an enhanced UART with 16 byte FIFOs, receive trigger levels, and data rates up to 1.5 Mbps.

  • Page 27: Real-Time Clock And Nvram

    Address Offset Function - 0xF1110000 0x0000 - 0x5FFF Available for users 0x0100 - 0x0200 VxWorks "bootline" 0x6000 - 0x6FFF Reserved (MOTLoad expansion) 0x7000 - 0x7FEF MOTLoad use (GEVs) 0x7FF0 0 0x7FFF Real Time Block MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 28 Introduction Introduction MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 29: Programming Details

    Chapter 2 Programming Details Overview This chapter includes additional programming information for the MVME6100 single board computer. The chapter discusses the following topics:  MV64360 Multi-Purpose Port Configuration on page 29  MV64360 Reset Configuration on page 31  Flash Memory on page 35 ...
  • Page 30 PCI Bus 0 Interrupt PCI-VME INT 0 (Tempe LINT0#, PMCspan INT 2#) PCI Bus 0 Interrupt PCI-VME INT 1 (Tempe LINT1#, PMCspan INT 3#) PCI Bus 0 Interrupt PCI-VME INT 2 (Tempe LINT2#, PMCspan INT 0#) MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 31: Mv64360 Reset Configuration

    Partial pin sample on deassertion of reset plus Serial ROM initialization via the I bus for user defined initialization The MVME6100 board supports both options. An on-board switch setting will be used to select the option. If the pin sample only method is selected, then states of the various pins on the device AD bus are sampled when reset is deasserted to determine the desired operating modes.

  • Page 32: Table 2-2 Mv64360 Power-Up Configuration Settings

    Default 0xf100.0000 Address 60x bus mode MPX bus mode CPU Bus AD[7:6] Resistor Configuration Reserved Reserved Calibration Disabled CPU Pads AD[8] Resistor Calibration Calibration Enabled Multiple Not supported AD[9] Fixed MV64360 Supported Support MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 33 DRAM clock AD[19] Resistor Address/Contr DRAM address and control ol Delay signals toggle on rising edge of DRAM clock Reserved DRAM control Two Pipe stages AD[21:20] Resistors path pipeline Reserved select Three pipe stages MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 34 MII/GMII TxD1[0] Resistor GMII/PCS Select Refer to MV64360 DRAM PLL N Specification MV-S100614- WE[3:0], Resistor Divider [7:4], 00 Rev. B (1/13/2003) page DP[3:0] [3:0] 144 for detail. MVME6100 is not using this mode. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 35: Flash Memory

    2.1.3 Flash Memory The MVME6100 contains two banks of flash memory accessed via the Device Controller bus contained within MV64360. Each bank contains from 8MB to 64MB of 32-bit wide Boot Block flash memory provided by two 16-bit wide Intel StrataFlash devices.

  • Page 36: Real-Time Clock And Nvram

    VPD and SPD EEPROMs contained on the MVME6100 to initialize the memory controller and other interfaces. For additional details regarding the MV64360 two-wire serial controller operation, refer to the MV64360 System Controller Data Sheet.

  • Page 37: Ddr Dram Serial Presence Detect

    This is a dual address serial EEPROM (AT24C64A or equivalent). 2.1.6 DDR DRAM Serial Presence Detect There are two on-board SPD serial EEPROMs on the MVME6100 accessible via the I serial interface. The first 128 bytes of each SPD contains module type, SDRAM organization, and timing parameters.

  • Page 38: Vpd And User Configuration Eeproms

    2.1.8 VPD and User Configuration EEPROMs The MVME6100 board contains an Atmel AT24C64 or compatible Vital Product Data (VPD) EEPROM containing configuration information specific to the board. Typical information that may be present in the VPD is: manufacturer, board revision, build version, date of assembly, memory present, options present, and L3 cache information.

  • Page 39: Pci Bus 0 And Pci Bus 1 Local Buses

    PCI6520, the Tsi148 ASIC, PMCspan slot and the PMC Slots. 2.1.12.1 PCI Mode/Frequency Selection The MVME6100 PCI Bus 0 bus is be set to PCI-X and 133 MHz for maximum performance. On-board logic drives the PCI-X initialization pattern, as defined by the PCI-X Addendum to the PCI Local Bus Specification Revision 1.0a at the rising edge of RST#.

  • Page 40: 2.1.12.3 Pci Arbitration Assignments For Mv64360 Asic

    (the MPP pins function as general purpose inputs). Software will configure the MPP pins to function as request/grant pairs for the internal PCI arbiter. The arbitration assignments on MVME6100 are as follows: Table 2-7 PCI Arbitration Assignments for MV64360 ASIC...

  • Page 41: 2.1.12.4 Pci Bus 1 Local Bus Pmc Expansion Slots

    Two PMC slots reside on the PCI Bus 1 local bus. The presence of PMCs can be positively determined by reading System Status Register 3. The INTA#, INTB#, INTC#, and INTD# from the PMC slots are routed by the MVME6100 as follows: Figure 2-1 PCI Bus 1 Local Bus PMC Expansion Slots 2.1.12.5 PCI Bus 0 Local Bus Devices...

  • Page 42: Mv64360 Interrupt Controller

    2.1.13 MV64360 Interrupt Controller The MVME6100 uses the MV64360 interrupt controller to route internal and external interrupt requests to the CPU and the PCI bus. The MV64360 interrupt controller registers are implemented as part of the CPU interface unit in order to have minimum read latency from CPU interrupt handler.

  • Page 43: Mv64360 Endian Issues

    Low Address register. This configurable setting allows a CPU access to PCI agents with a different endianess convention. Refer to the MV64360 Data Sheet, listed in Appendix A, Related Documentation, for additional information and programming details. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 44 Programming Details Programming Details MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)

  • Page 45: Related Documentation

    Table A-1 SMART EC Publications Document Title Publication Number MVME6100 Data Sheet MVME6100-DS MVME6100 Single Board Computer Installation and Use 6806800D58E MOTLoad Firmware Package User’s Manual 6806800C24C IPMC7126E/7616E I/O Module Installation and Use 6806800A45B PMCspan PMC Adapter Carrier Board Installation and Use Manufacturers’...

  • Page 46: Table A-3 Related Specifications

    Table A-3 Related Specifications Document Title and Source Publication Number VITA http://www.vita.com/ VME64 Specification ANSI/VITA 1-1994 VME64 Extensions ANSI/VITA 1.1-1997 2eSST Source Synchronous Transfer VITA 1.5-199x MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 47 IEEE - Common Mezzanine Card Specification (CMC) Institute of P1386 Draft 2.0 Electrical and Electronics Engineers, Inc. IEEE - PCI Mezzanine Card Specification (PMC) Institute of P1386.1 Draft 2.0 Electrical and Electronics Engineers, Inc. MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 48 Related Documentation MVME6100 Single Board Computer Programmer’s Reference (6806800J39C)
  • Page 50 © 2019 SMART Embedded Computing™, Inc. All rights reserved. The stylized “S” and “SMART” is a registered trademark of SMART Modular Technologies, Inc. and “SMART Embedded Computing” and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies, Inc. All other names and logos...

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