Pld Watchdog Control Register; Pld Watchdog Timer Count Register; Table 5-20 Pld Watchdog Control Register; Table 5-21 Pld Watchdog Timer Count Register - SMART Embedded Computing MVME2500 Installation & Use Manual

Memory Maps and Registers
5.5.17

PLD Watchdog Control Register

The MVME2500 provides a watchdog control register.

Table 5-20 PLD Watchdog Control Register

REG PLD Watch Dog Timer Load - 0xFFC80604
Bit 15
Watchdog_
Field
EN
OPER R/W
RESET 0000
Field Description
EN Enable. If cleared, the watchdog timer is disabled. If set, the watchdog timer is enabled.
5.5.18

PLD Watchdog Timer Count Register

The MVME2500 provides a watchdog timer count register.

Table 5-21 PLD Watchdog Timer Count Register

REG
Bit
Field
OPER
RESET
Field Description
Count
102
14 13 12 11
RS RS RS RS
VD VD VD VD
R
PLD Watchdog Timer Count - 0xffc80606
15:0
Count
R/W
0xEA60 (60secs)
These bits define the watchdog timer count value. When the watchdog counter is
enabled, it will count up from zero (reset value) with a 1 ms resolution until it
reaches the COUNT value set by this register. Watchdog will generate a soft reset
signal if it bites.
Setting this register to 0xEA60 or 60,000 counts will provide a watchdog timeout of
60 seconds.
10 9 8 7 6
RS RS RS RS RS
VD VD VD VD VD
MVME2500 Installation and Use (6806800L01S)
Memory Maps and Registers
5 4 3 2 1
RS RS RS RS RS
VD VD VD VD VD
0
RS
VD