SMART Embedded Computing MVME2500 Installation & Use Manual page 120

Programming Model
Table 7-1
CONFIG
ETSEC3
23
Protocol
BOOT
24 ROM
Location
Host/Agent
25
Config
I/O Port
26
Select
DDR
27 SDRAM
TYPE
SerDes PLL
28 Time Out
Enable
System
29
Speed
SDHC Card
30 Detect
Polarity
RAPID
31 System
Size
120
POR Configuration Settings (continued)
CONFIG PINS
UART_RTS0,
UART_RTS1
TSEC1_TXD[6:4],
TSEC1_TX_ER
LWE1/LBS1,
LA[18:19]
TSEC1_TXD[3:1],
TSEC2_TX_ER
TSEC2_TXD1
TRIG_OUT
LA[28]
TSEC2_TXD_5
CONFIG SELECTION
The eTSEC3 controller
operates using the
10 RGMII protocol if not
configured to operate in
SGMII mode.
On-chip boot ROM-SPI
011X configuration (x=0),
SDHC (x=1)
The processor acts as
the host/root complex
111 for all PCI-E/Serial
Rapid IO interfaces
(default).
PCI-E 1 (x1) (2.5 Gbps)
- SerDes lane 0
PCI-E 2 (x1) (2.5 Gbps)
0010
- SerDes lane 2
PCI-E 3 (x2) (2.5 Gbps)
- SerDes lane 2-3
DDR31.5 V. CKE low at
1
reset (default)
Disable PLL lock time-
out counter. The power-
on-reset sequence waits
1
indefinitely for the
SerDes PLL to lock
(default).
SYSCLOCK is above 66
1
MHz
1 Not Inverted
Default
MVME2500 Installation and Use (6806800L01S)
Programming Model
REMARKS
RapidIO is not used