Memory Maps And Registers; Overview; Memory Map; Table 5-1 Physical Address Map - SMART Embedded Computing MVME2500 Installation & Use Manual

Memory Maps and Registers

5.1

Overview

System resources including system control and status registers, external timers, and the
QUART are mapped into 16MB address range accessible from the MVME2500 local bus
through the P20x0 QorIQ LBC.
5.2

Memory Map

The following table shows the physical address map of the MVME2500.
Table 5-1
Device Name
DDR
PCIE 3 Mem
PCIE 2 Mem
PCIE 1 Mem
PCIE 3 IO
PCIE 2 IO
PCIE 1 IO
UART0
UART1
UART2
UART3
Timer
FPGA
CCSR
MRAM
MVME2500 Installation and Use (6806800L01S)
Physical Address Map
Start Address
0x0000_0000
0x8000_0000
0xa000_0000
0xc000_0000
0xffc0_0000
0xffc1_0000
0xffc2_0000
0xffc4_0000
0xffc5_0000
0xffc6_0000
0xffc7_0000
0xffc8_0000
0xffdf_0000
0xffe0_0000
0xfff0_0000
End Address
0x7fff_ffff
0x9fff_ffff
0xbfff_ffff
0xdfff_ffff
0xffc0_ffff
0xffc1_ffff
0xffc2_ffff
0xffc4_ffff
0xffc5_ffff
0xffc6_ffff
0xffc7_ffff
0xffc8_ffff
0xffdf_0fff
0xffef_ffff
0xfff7_ffff
Chapter 5
Size
2GB
512MB
512MB
512MB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
4KB
1MB
512KB
89