Security Engine (Sec) 3.1; Common On-Chip Processor (Cop); P20X0 Hardware Configuration Pins; System Memory - SMART Embedded Computing MVME2500 Installation & Use Manual

4.2.12

Security Engine (SEC) 3.1

The integrated security engine of the P20x0 is designed to off-load intensive security
functions like key generation and exchange, authentication and bulk encryption from the
processor core. It includes eight different execution units where data flows in and out of an
EU.
4.2.13

Common On-Chip Processor (COP)

The COP is the debug interface of the QorIQ P20x0 processor. It allows a remote computer
system to access and control the internal operation of the processor. The COP interface
connects primarily through the JTAG and has additional status monitoring signals. The
COP has additional features like breakpoints, watch points, register and memory
examination/modification and other standard debugging features.
4.2.14

P20x0 Hardware Configuration Pins

A series of strapping pins are required to initialize the P20x0. These pins are samples
during the assertion of HRESET and return to their assigned function after HRESET is
deasserted.
4.3

System Memory

The processors integrated memory controller supports both DDR2 and DDR3 memory
devices. It has one channel and can be configured up to four memory banks with x8, x16
and x32 devices. Using 4GB devices allows support of up to 16GB of memory.
The MVME2500 has total of eight board variants, half of which has soldered 2GB memory,
while the remaining half has 16GB memory. The x8 or 1 Gbit device forms 2GB and 1GB
memory capacity. A total of 16 devices for 2GB and eight devices are used to form 16GB.
MVME2500 supports ENP1 and ENP2 operating environment. The ENP1 environment
uses Samsung for all variants including the commercial grade devices, while the ENP2
variants use Micron.
4.4

Timers

There are various timer functions implemented on the MVME2500 platform.
MVME2500 Installation and Use (6806800L01S)
Functional Description
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