Clock Distribution; Table 7-6 Clock Distribution - SMART Embedded Computing MVME2500 Installation & Use Manual

7.7

Clock Distribution

The clock function generates and distributes all of the clocks required for system operation.
The ICS9FG108 is used to generate all the required PCI-E clocks. The 25MHz clocks for
the Ethernet PHY and SATA bridge are supplied by ICS83905 device. Most of the QorIQ
P2020 clocks are generated by ICS840S07I device. Additional clocks required by individual
devices are generated near the devices using individual oscillators. The following table lists
the clocks required on the MVME2500 along with the frequency and source.
Table 7-6
Device
QorIQ P20x0
QorIQ P20x0
QorIQ P20x0
QorIQ P20x0
ICS840S07I
88SE6121
ICS9FG108
BCM54616S
BCM54616S
BCM54616S
XMC
QorIQ P20x0
TSI384
TSI384
88SE6121
FPGA
USB
QorIQ P20x0
PMC
MVME2500 Installation and Use (6806800L01S)
Clock Distribution
Clock Signal
CPU_SYSCLK
CPU_DDR_CLK
CLK_PCI_BR3
EC_GTX_CLK125
CLK_25MHZ_ICS840S07
CLK_88SE6121_25MHZ
CLK_25MHZ_ICS9FG108
BP_PHY_25MHZ_CLK
FP_PHY_25MHZ_CLK
SW_25MHZ_CLK
CLK_XMC1
SD_REF_CLK
CLK_PCIEC1
CLK_PCIEC3
CLK_88SE6121_PCIE_
100MHZ
CLK_CPLD
CLK_USB_1_24MHZ
CPU_RTC
CLK_PMC1
Programming Model
Clock Tree
Frequency
Source
100MHz ICS840S07I
100MHz ICS840S07I
133MHz ICS840S07I
125MHz ICS840S07I
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
100MHz ICS9FG108
100MHz ICS9FG109
100MHz ICS9FG110
100MHz ICS9FG111
100MHz ICS9FG112
1.8432MHz Oscillator
24MHz Oscillator
1MHz FPGA
33/66/100/133
TSI384
MHz
VIO
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
DIFF
DIFF
DIFF
DIFF
DIFF
+3.3V
+3.3V
+3.3V
+3.3V
125