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Functional Description
4.17.1
Reset Sequence
The timing of the reset sequence supports each chip reset requirements with respect to the
power supply.
All the resets are controlled by the FPGA with a power supply of +3.3V from+5V. All the
resets are asserted until +1.5V power is Good. Initially peripherals resets are released to
corresponding sequence, then later the CPU reset is released. Once the CPU reset is
released, the CPU starts boot up sequence.
Below is the SW event sequence from the release of CPU reset to boot up.
1. Copying of U-boot from SPI to CPU cache.
2. Initialization of Serial Console.
3. Initialization of DDR using SPD parameters in cache.
4. Execution relocation to RAM.
5. Initialization of PCI.
6. POST routine.
7. Additional SW routines.
8. U-boot terminal visibility, ready to load OS image.
MVME2500 Installation and Use (6806800L01S)
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