Pld Test Register 1; Table 5-15 Pld Test Register 1 - SMART Embedded Computing MVME2500 Installation & Use Manual

Memory Maps and Registers
I2C_1_D
I2C_1_C
When SERIAL_FLASH_WP is set to Low, this port will automatically read as low due
to AND connection between the two ports.
5.5.12

PLD Test Register 1

The MVME2500 PLD provides an 8-bit general purpose read/write register which is used
by the software for PLD testing or general status bit storage.

Table 5-15 PLD Test Register 1

REG
Bit
Field
OPER
RESET
Field Description
TEST_REG1
98
I2C debug port-Data
I2C_DEBUG_EN=0
I2C_DEBUG_EN-1
I2C debug port-Clock
I2C_DEBUG_EN=0
I2C_DEBUG_EN-1
PLD Test Register 1- 0xFFDF0080
7 6 5
TEST_REG1
R/W
00
General purpose 8-bit R/W field
HiZ - Tri-Stated
1 - Driven High
0 - Driven Low
HiZ - Tri-Stated
1 - Driven High
0 - Driven Low
4 3 2
MVME2500 Installation and Use (6806800L01S)
Memory Maps and Registers
1 0