Pld U-Boot And Tsi Monitor Register; Pld Boot Bank Register; Table 5-12 Pld U-Boot And Tsi Monitor Register; Table 5-13 Pld Boot Bank Register - SMART Embedded Computing MVME2500 Installation & Use Manual

Memory Maps and Registers
5.5.9

PLD U-Boot and TSI Monitor Register

The MVME2500 PLD provides an 8-bit register which indicates the status of the U-Boot's
normal environment switch and TSI interface signals.

Table 5-12 PLD U-Boot and TSI Monitor Register

REG
Bit
Field
OPER
RESET
Field Description
BDFAIL_N
NORMAL_ENV
SCON
5.5.10

PLD Boot Bank Register

The MVME2500 PLD provides an 8-bit register which is used to declare successful U-Boot
loading, indicating the SPI boot bank priority and actual SPI bank it booted from.

Table 5-13 PLD Boot Bank Register

REG
Bit
Field
OPER
RESET
96
PLD PCI_PMC_XMC_MNTR - 0xFFDF001F
7 6 5
RSVD RSVD RSVD RSVD
R
0 0 0
TSI148 BDFAIL_N Pin out
1 - No TSI Fail
0 - TSI Fail
Normal Environment Switch Indicator
1 - Use safe ENV
0 - Use normal ENV
System Controller Indicator
1 - System Controller
0 - Non-system Controller
PLD Boot Bank - 0xFFDF0050
7 6 5
SPI_GOODReg
(write 0xA4 into this reg to indicate successful loading of the U-
Boot.
R/W
0 0 0
4 3 2
RSVD BDFAIL_N
0 0 X
4 3
0 0
MVME2500 Installation and Use (6806800L01S)
Memory Maps and Registers
1 0
NORMAL_ENV SCON
X X
2 1 0
BOOT_B BOOT_S
LOCK_A PI
R R
0 X 0