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Functional Description
2
4.2.6
I
C Interface
The MVME2500 uses only one of the two independent I
more information, see
4.2.7
USB Interface
The P20x0 implements a USB 2.0 compliant serial interface engine. For more information,
see
USB on page
4.2.8
DUART
The chipset provides two universal asynchronous receiver/transmitter (UART), each of
which acts independently of the other. Each UART is clocked by the CCB clock and is
compatible with PC16522D. As a full-duplex interface, it provides a 16-byte FIFO for both
transmitter and receiver mode.
4.2.9
DMA Controller
The DMA controller transfers blocks of data between the various interfaces and functional
blocks of P20x0 that are independent of the e500 cores. The P20x0 DMA controller has
three high-speed DMA channels, all of which capable of complex data movement and
advanced transaction chaining.
4.2.10
Enhanced Three-Speed Ethernet Controller (eTSEC)
The eTSEC controller of the device communicates to the 10Mbps, 100Mbps, and 1Gbps
Ethernet/IEE 802.3 networks, as well as to devices with generic 8 to 16-bit FIFO ports. The
MVME2500 uses the eTSEC using the RGMII interface.
4.2.11
General Purpose I/O (GPIO)
The P20x0 has a total of sixteen I/O ports. Four of these ports are used alternately as
external input interrupt. All sixteen ports have open drain capabilities.
The P20x0 processor provides a Serial Rapid I/O interface. However, this interface is
not utilized by the MVME2500.
70
I2C Devices on page
78.
2
C buses on the processor. For
78.
MVME2500 Installation and Use (6806800L01S)
Functional Description
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