Chipset; E500 Processor Core; Integrated Memory Controller - SMART Embedded Computing MVME2500 Installation & Use Manual

Functional Description
4.2

Chipset

The Product Type utilizes the QorIQ P20x0 integrated processor. It offers an excellent
combination of protocol and interface support which includes the following components:
QorIQ P20x0 integrated processor or e500v2 processor core (P2020) and a single

e500v2 processor core (P2010).
PCI Express interface

Local Bus Controller

Secure Digital Host Controller

2
I

USB interface

DUART

DMA controller

Enhanced three speed Ethernet controller

General Purpose I/O (GPIO)

Integrated Security Engine

Common On-chip Processor

P20x0 Strapping pins

4.2.1

e500 Processor Core

The QorIQ integrated processors offer dual high performance e500v2 core (P2020) and a
single e500v2 core (P2010). It operates from 800MHz up to 1.2GHz core frequency. The
e500 processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processor that implement the Book E definition of the
PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture
using the lower words of 64-bit general-purpose registers (GPRs) while E500v2 uses 36-bit
physical addressing.
4.2.2

Integrated Memory Controller

A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and
DDR3 memories available. Unbuffered registered DIMMs are also supported. A built-in
error checking and correction (ECC) ensures very low bit-error rates for reliable high-
frequency operation. Though ECC is not implemented on MVME2500, the board includes
a place holder for additional chips for ECC whenever it is needed in the future.
68
C interface
MVME2500 Installation and Use (6806800L01S)
Functional Description