Parallel Trace Modeling - ARM DSTREAM-PT Reference Manual

System and interface design
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3.4

Parallel trace modeling

For trace bit rates of 0-600Mbps, basic signal integrity can be established using simplified modeling.
Most of the transmission line model consists of the cable that is used to connect the DSTREAM-ST unit
to the target.
The 30cm CoreSight cable is made using 0.635mm pitch ribbon, and can be modeled as a 66Ω
transmission line, with a 1.5ns propagation delay, and 0.4Ω DC resistance. The connectors at either
end of the cable can be modeled as a 0.5pF capacitance to ground.
The 15cm CoreSight cable is made using 0.635mm pitch ribbon, and can be modeled as a 66Ω
transmission line, with a 0.75ns propagation delay, and 0.2Ω DC resistance. The connectors at either
end of the cable can be modeled as a 0.5pF capacitance to ground.
The JTAG 20 cable is made using 1.27mm pitch ribbon, and can be modeled as a 100Ω transmission
line, with a 1.5ns propagation delay, and 0.1Ω DC resistance. The connectors at either end can be
modeled as a 1.0pF capacitance to ground.
The MIPI-60 cable is made using 0.5mm pitch micro-coaxial ribbon, and can be modeled as a 50Ω
transmission line, with a 1.5ns propagation delay, and 0.1Ω DC resistance. The connectors at either
end can be modeled as a 0.25pF capacitance to ground.
The circuit at the DSTREAM-ST end of the transmission line can be modeled using the following
primitives:
All resistors can be modeled as their ideal resistance values with minimum or zero parasitics.
All capacitors can be modeled as their ideal capacitance values with minimum or zero parasitics.
Input comparators can be modeled using the Spartan 3 SSTLx_I model. The switching threshold can
be assumed to be half of the VTREF voltage, as supplied by the target. The data is valid when it is
100mV above or below this threshold.
Output drivers can be modeled using the Spartan 3 LVCMOS Fast 16mA model. You must choose
the model voltage to match the target system voltage.
All other parasitics and traces within the DSTREAM-ST are negligible for most purposes.
To achieve good signal integrity, Arm recommends using series termination resistors on all target
outputs.
101714_0100_02_en
Note
Copyright © 2019 Arm Limited or its affiliates. All rights reserved.
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3 Target board design
3.4 Parallel trace modeling
3-59

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