ARM DSTREAM-PT Reference Manual page 6

List of Figures
Arm DSTREAM-PT System and Interface Design
®
Reference Guide
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 1-7
Figure 1-8
Figure 1-9
Figure 1-10
Figure 1-11
Figure 1-12
Figure 1-13
Figure 1-14
Figure 1-15
Figure 1-16
Figure 1-17
Figure 1-18
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
101714_0100_02_en
Simple JTAG connection ....................................................................................................... 1-13
Chained JTAG connection ..................................................................................................... 1-14
JTAG timing diagram ............................................................................................................. 1-15
Basic JTAG port synchronizer ............................................................................................... 1-16
Timing diagram for the Basic JTAG synchronizer .................................................................. 1-16
JTAG port synchronizer for single rising-edge D-type ASIC design rules ............................. 1-16
Timing diagram for the D-type JTAG synchronizer ................................................................ 1-17
Example reset circuit ............................................................................................................. 1-20
SWD timing diagrams ............................................................................................................ 1-22
TRACECLK timing diagram ................................................................................................... 1-25
Target interface logic levels ................................................................................................... 1-27
Input/Output signals ............................................................................................................... 1-28
TCK signal ............................................................................................................................. 1-28
Reset signals ......................................................................................................................... 1-28
Trace signals .......................................................................................................................... 1-29
VTREF signals ....................................................................................................................... 1-29
Typical SWD circuit ................................................................................................................ 1-30
Typical JTAG circuit ............................................................................................................... 1-31
Arm JTAG 20 connector pinout .............................................................................................. 2-35
CoreSight 10 connector pinout .............................................................................................. 2-36
CoreSight 20 connector pinout .............................................................................................. 2-37
TI JTAG 14 connector pinout ................................................................................................. 2-39
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