Chapter 1
Debug and trace interface
The Arm debug and trace interface enables powerful software debug and optimization on an Arm
processor-based target system. It is based on the IEEE 1149.1 (JTAG) interface coupled with various
additional signals. This chapter introduces these signals and describes their use within the interface.
•
Unless otherwise specified, all pull-up/pull-down resistors that are discussed in this chapter must be
between 1K and 100K (10K is recommended).
•
Unless otherwise specified, any signals beginning with a lowercase 'n' are, by default, active-
It contains the following sections:
•
1.1 JTAG signals on page
•
1.2 Return Clock (RTCK) signal on page
•
1.3 Reset signals on page
•
1.4 Run-Control signals on page
•
1.5 Serial Wire Debug (SWD) signals on page
•
1.6 Trace signals on page
•
1.7 Target Voltage Reference (VTREF) signals on page
•
1.8 I/O diagrams for DSTREAM-PT signals on page
•
1.9 Typical SWD circuit on page
•
1.10 Typical JTAG circuit on page
101714_0100_02_en
Note
1-13.
1-19.
1-21.
1-24.
1-30.
Copyright © 2019 Arm Limited or its affiliates. All rights reserved.
1-18.
1-22.
1-26.
1-28.
1-31.
Non-Confidential
.
LOW
1-12