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QB-V850MINIL, QB-V850MINI Emulator
3.5.4
Connecting the RESET# signal (for V850E2, V850E1, or V850ES)
This is the system reset input signal. QB-V850MINIL or QB-V850MINI controls the RESET# signal as follows.
RESET#
Hi-Z
Connect the RESET# signal as shown in Figure 3-16 if any of the conditions listed below is satisfied. At this time,
make sure that the RESET# signal does not conflict with the RESET# signal generated on the target system. When
none of the following conditions are satisfied, leave open the pin for the RESET# signal that is output from
QB-V850MINIL or QB-V850MINI.
• The target device should be kept in the reset state before debugger startup or after debugger termination.
• The OCD signal pins (DCK, DDI, DDO, DMS, and DRST#) are alternate-function pins in the specifications of the
target device, the OCD signal becomes inactive due to a reset by other than the RESET# pin, and the OCD signals are
not set to active in the startup routine.
For example, when using a device in which the pins that alternately function as the OCD signal pins are controlled by
the OCDM0 register as shown below, the OCDM0 register is cleared to 0 upon reset by POC, so the OCD signals are
not specified and as a result, on-chip debugging cannot be performed normally.
OCDM
OCDM0
Remark
R20UT0221EJ0400 Rev.4.00
2013.08.30
Target system power turned on
Software starts up (debugger starts running)）
Low level
Hi-Z
Figure 3-15. Timing of RESET# on QB-V850MINIL or QB-V850MINI
7
6
0
0
Specification of alternate-function pin for on-chip debug function
0
Use as port/peripheral function pin
1
Use as on-chip debug function pin
Initial value At RESET# pin input: OCDM0 = 1
After reset by POC: OCDM0 = 0
After internal reset (other than POC): The OCDM register holds the value before reset
Software terminates (debugger stops running)
Low level
Hi-Z
5
4
3
0
0
0
3. On-Chip Debugging
Target system power turned off
2
1
0
0
Page 42 of 86
0
OCDM0
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