Cautions On Target System Design (For V850E2, V850E1, Or V850Es) - Renesas QB-V850MINIL User Manual

QB-V850MINIL, QB-V850MINI Emulator
3.5.2

Cautions on target system design (for V850E2, V850E1, or V850ES)

Note the following points when designing the target system circuits and the board.
Keep the pattern length as short as possible.
（1）
If V is between 2.0 and 5.5 V, it is judged that target system power is being supplied, and the signals switch to
（2）
DD
being used as debug signals. If V
configured correctly, regardless of whether target system power is being supplied or not. In this case, the DRST#,
DCK, DMS, DDI, FLMD0, and RESET# pins become high impedance, regardless of the operating status of the
debugger. To avoid this, be sure to input the voltage from the power supply pin on the target device directly to
V .
DD
The circuit for connecting FLMD0 varies when using flash self programming or using microcontrollers that do not
（3）
have an on-chip flash memory. See 3.5.3 Connecting the FLMD0 signal (for V850E2, V850E1, or V850ES)
for details.
To reset the target device while the target system power supply is on, connect the RESET# signal. See 3. 5. 4
（4）
Connecting RESET# signal (for V850E2, V850E1, or V850ES) for details.
R20UT0221EJ0400 Rev.4.00
2013.08.30
is not between 2.0 and 5.5 V, it is judged that the system has not been
DD
3. On-Chip Debugging
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