Verifying - Xilinx EZTag User Manual

following command at the operating system prompt.
When you do not specify any options, the EZTag software selects the
port where the cable is connected and sets the baud rate to the
maximum allowed by the platform. You can modify the
communication port and baud rate by changing the appropriate
settings in the xchecker.pro file.
1. To download in an interactive mode, enter the following
2.
3. To program the a design, enter this command string:

Verifying

After you have properly configured a device, you can verify its
configuration and compare it to your original design.
In most applications, verification is not needed, but this feature can
be helpful with designs that experience extremely unstable or noisy
V
To download and verify a design, enter the following command
string at the operating system prompt.
Specifying the –v option causes the XChecker cable to download the
EZTag User Guide
eztag design_name
command at the system prompt.
eztag
You see the following message on the screen:
Xilinx (R) EZTAG XC9500-Pre-Release-V2.0.a-JTAG
Boundary-Scan Download
Copyright (C) Xilinx, Inc. 1991-1995. All rights
reserved.
Cable ID type is 'XCHECKER'
Cable is connected to '/dev/ttya'
Baud rate is 38400
To specify the number, type, names and order of devices in the
boundary-scan chain:
part_type
part :
program design_name
conditions.
CC
eztag –v design_name
EZTag with Workstations
design_name
4-3