Xilinx EZTag User Manual page 21

Figure 2-2 show top and bottom views of the XChecker cable.
XChecker Cable
Figure 2-2 XChecker Cable
The cable assembly houses internal circuitry consisting of a Xilinx
FPGA and a static RAM. The internal Xilinx FPGA functions as an
interface between the XChecker software and the target system. The
static RAM stores data for readback.
You can use the XChecker cable with a single EPLD or several
connected in a boundary-scan chain to download and readback
configuration data.
The XChecker cable transmits configuration data to all target EPLDs
at 921 kHz.
Communication between the host system and the XChecker cable is
dependent on host system capability. Table 2-1 lists the valid baud
rates for serial cables using the supported platforms. Parallel cables
will support the transfer rate your system uses.
When the XChecker cable is used to drive a JTAG TAP, a special
configuration file "xckjtag.sys" is downloaded automatically to the
FPGA in the cable assembly. This configuration file converts the
FPGA into a special-purpose JTAG TAP processing unit. Special
instructions sent to the FPGA via the serial port sequence the TAP to
exercise the target system JTAG circuitry. TDO data is captured in the
XChecker's static RAM. This can then be uploaded to the host via the
EZTag User Guide
TM
Header 2
Header 1
CAUTION
RT
Model: DLC4
RD
Power: 5V 100mA Typ. TRIG
Serial: DL- 12345
TDI
TCK
TMS
SENSITIVE
ELECTRONIC
TM CLKI
DEVICE
Made in U.S.A.
CLKO
EZTag Download Cable Options
Top View
VCC
GND
Bottom View
CCLK
D/P
DIN
PROG
INIT
RST
X2580
2-3