Xilinx EZTag User Manual

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Download this manual

ON LIN E

EZTAG

US E R GUIDE

TA BL E O F CO NT E NT S

IND E X

GO T O O T H E R B OOK S

™

0 4 0 1405

Table of Contents

Need help?

Do you have a question about the EZTag and is the answer not in the manual?

Questions and answers

Summary of Contents for Xilinx EZTag

Page 1 ON LIN E EZTAG US E R GUIDE TA BL E O F CO NT E NT S IND E X GO T O O T H E R B OOK S ™ 0 4 0 1405...
Page 2 EZTag User Contents Guide Introduction EZTag Download Cable Options In-System Tutorial for PCs EZTag with Workstations Error Messages EZTag User Guide Printed in U.S.A.
Page 3 Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
Page 4: Manual Contents
Before using this manual, you should be familiar with the operations that are common to all Xilinx’s software tools: how to bring up the system, select a tool for use, specify operations, and manage design data. These topics are covered in the Development System Reference Guide.
Page 5 [ • Braces “{ }” enclose a list of items from which you choose one or more. designname xnfprep ignore_rlocs={true|false} • A vertical bar “|” separates items in a list of choices. editor symbol [bus|pins] EZTag User Guide...
Page 6 A vertical ellipsis indicates repetitive material that has been omitted. IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ • A horizontal ellipsis “. . .” indicates that the preceding can be repeated one or more times. blockname loc1 loc2 locn allow block Xilinx Development System...
Page 7: Table Of Contents
Modifying a Programmed Design File ........... 1-8 BSDL Summary ................1-8 JEDEC 3C Summary ..............1-9 Chapter 2 EZTag Download Cable Options XChecker Hardware (Serial) ............2-1 Connecting the XChecker Cable........... 2-4 Connecting the XChecker Cable to Your Workstation ..... 2-4 Connecting the XChecker Cable to Your PC ......
Page 8 Delete ................. 3-6 Saving a Chain................. 3-7 Saving a Modified Chain ............3-8 Data Security Selection............3-8 Chapter 4 EZTag with Workstations Using the EZTag Software ............4-1 EZTag Files................4-1 design.jed ................4-2 eztag.pro................4-2 batch_file.cmd..............4-2 device.bsd................4-2 Invoking EZTag................
Page 9 Sys —Temporarily Exit to Operating System ......4-12 Verify — Verify Target EPLD Bitstream........4-12 Troubleshooting Guide..............4-13 Communication................. 4-13 Improper Connections .............. 4-14 Improper or Unstable VCC ............4-14 Appendix A Error Messages Introduction ..................A-1 Error Messages................A-1 EZTAG User Guide...
Page 10: Introduction
Chapter 1 Introduction This chapter introduces you to the basic concepts of Xilinx JTAG capabilities and the XC9500 series products. Boundary Scan What is IEEE 1149.1 Design complexity, difﬁculty of loaded board testing, and the limited pin access of surface mount technology led industry leaders to seek accord on a standard to support the solution of these problems.
Page 11: How Does It Work
1 to the system if the pin is not driven. TDI -this pin is the serial data input to all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register Xilinx Development System...
Page 12: Jtag Tap Controller
JTAG TAP Controller The JTAG TAP Controller is a 16-state ﬁnite state machine, that controls the scanning of data into the various registers of the JTAG architecture. A state diagram of the TAP controller is shown in Figure EZTag User Guide...
Page 13: Jtag Tap Controller States
Exit1-DR. This is a temporary state that allows the option of passing on to the Pause-DR state or transitioning directly to the Update-DR state. Pause-DR. This is a wait state that allows shifting of data to be temporarily halted. Xilinx Development System...
Page 14: Jtag Instructions Supported In Fastflash Parts
JTAG Instructions Supported in FastFLASH Parts Mandatory Boundary Scan Instructions BYPASS. The BYPASS instruction allows rapid movement of data to and from other components on a board that are required to perform test operations. EZTag User Guide...
Page 15: Optional Boundary Scan Instructions
FVFY. The FVFY instruction is used to read the programming of the fuse locations at a speciﬁed address. ISPLD. The ISPLD instruction loads the programmed values into the device memory. It then activates the device to operate according to the programmed values. Xilinx Development System...
Page 16: Device Operations
Readback. Reads back the contents of device programming registers and creates a new JEDEC ﬁle with the results. Checksum. Reads back the contents of device programming registers and calculates a checksum for comparison against the expected value. EZTag User Guide...
Page 17: Data Security
BSDL ﬁle is required for each kind of boundary-scan device in the system. The BSDL ﬁles for FastFLASH devices are provided as part of the product release. The user is responsible for providing BSDL ﬁles for any non-FastFLASH parts used in the boundary-scan chain. Xilinx Development System...
Page 18: Jedec 3C Summary
The system looks for the JEDEC ﬁles along the XACT path and in the current working directory. The name of the JEDEC ﬁle is assumed to be < design name >.jed, but can be speciﬁed exactly by the user. EZTag User Guide...
Page 19: Eztag Download Cable Options
EZTag to download, read back, verify design conﬁguration data for any device, and to probe internal logic states of an EPLD design. Two cables are available from Xilinx. The ﬁrst is a serial RS-232 known as the XChecker that you can connect to a serial port. The second is the Parallel Download Cable that you can connect to a printer port.
Page 20 EZTag User Guide 2-1 shows the XChecker cable hardware and accessories. Keyed Connection to Target System Connection to Host Computer DB-25 Connector DB-9 Connector Connect to FPGA Demo Board Test Fixture Enlarged to show mating plugged slots May be required to connect...
Page 21 Figure 2-2 XChecker Cable The cable assembly houses internal circuitry consisting of a Xilinx FPGA and a static RAM. The internal Xilinx FPGA functions as an interface between the XChecker software and the target system. The static RAM stores data for readback.
Page 22: Connecting The Xchecker Cable
On PCs you can connect a serial XChecker cable connects to your system RS232 serial port (you may need a DB9/DB25 adapter). The EZTag software will automatically identify thy XChecker cable when correctly connected to your PC. If you choose to, you may also select this connection manually.
Page 23: Connection To Your Target System
EZTag Download Cable Options Connection to Your Target System You need appropriate pins on the target system for connecting the target system board to the header connection on the cable. These connectors must be standard 0.025−inch square male pins that have dedicated traces to the target system control pins.
Page 24 EZTag User Guide Each pin has a 100-Ω series resistor. You must provide an external pull-up resistor (approximately 10-50-kΩ) where indicated. Table 2-2 describes the pin connections to the target circuit board. Table 2-2 XChecker Cable Connections and Deﬁnitions Name...
Page 25: Connecting For System Operation
EZTag Download Cable Options Name Function Connections Not used. Unconnected. Not used. Unconnected. TRIG Not used. Unconnected. Connecting for System Operation Connect the XChecker cable to the host system and your target system as shown in Figure 2-3. NOTES: 1. D/P XC4000\XC5200 2.
Page 26: Parallel Download Cable
EZTag User Guide Parallel Download Cable The Parallel Download Cable consists of a cable assembly containing logic to protect your PC‘s parallel port and a set of headers to connect to your target system. Using the Parallel Download Cable requires a PC equipped with an AT compatible parallel port interface with a DB25 standard printer connector.
Page 27: Connecting The Parallel Download Cable
Connecting the Parallel Download Cable On PCs you can connect the parallel cable to your system’s parallel printer port. The EZTag software will automatically identify the cable when correctly connected to your PC. If you choose to, you may also select this connection manually.
Page 28: Flying Lead Connectors
EZTag User Guide Flying Lead Connectors The ﬂying lead connector is two ﬂying lead header connectors with eight standard individual female connectors on one end that ﬁt onto 0.025″ square male pins. Each lead is labeled to identify the proper pin connection.
Page 29: Connecting For System Operation
EZTag Download Cable Options Name Function Connections Test Mode Select – this sig- Connect to system nal is decoded by the TAP TMS pin. controller to control test operations. Connecting for System Operation Connect the parallel cable to the host system and your target system as shown in Figure 2-5.
Page 30: In-System Tutorial For Pcs Introduction
Next connect the JTAG TAP inputs. Connect TCK, TDI, TMS and TDO to the target board. TRST is not supported by the XC9500 EZTAG Download Cable. If any of your JTAG parts have a TRST pin, it should be connected to VCC.
Page 31: Selecting A Port For The Cable
Attach lead’s connector to ﬁrst row of pins Figure 3-1 EZTAG Cable and Leads Selecting a Port for the Cable You may select a serial or parallel port for your cable from the EZTag Interface. To set up a parallel port: Cable...
Page 32: Configuring A Device In-System
Make sure the cable is attached properly and the target board is turned on. Memory FPGA CPLD System Logic EZTAG Cable Target Figure 3-3 JTAG Connections Make sure that the BSDL ﬁles for non-XC9500 devices are stored along the XACT search path. EZTag User Guide...
Page 33 EZTag User Guide Invoke the EZTAG-JTAG Download Software menu by double- clicking the EZTAG-JTAG Download Software icon. Figure 3-4 EZTAG Menu with U1 Set for Programming and U2 Set in Bypass Mode. Select the operations desired for each XC95108 part.
Page 34: Modifying A Chain
Note: It will take between thirty and sixty seconds to download to a part using the Silicon Evaluation Release software. Modifying a Chain The Chain Editing Operations are located on the EZTAG menu. They softkeys listed as Insert, Change, and Delete. In EZTag User Guide...
Page 35: Insert
EZTag User Guide addition, if you want to start over, you can use File Clear Chain. This will clear all entries in the Chain Description. Insert The insert softkey allows you to insert a new device into the chain. When you insert, the device number selected and all subsequent devices are moved down one in the chain.
Page 36: Saving A Chain
Note: When no chain editing operation is active, selected ﬁles (by double-clicking) are added to the end of the chain. Saving a Chain To save an EZTAG chain description for later use, create a Chain Description File (.cdf) using: File Save A screen titled CDF File Operation will appear.
Page 37: Saving A Modified Chain
OK. Data Security Selection Any Xilinx device selected for programming can be secured with the Data Security (DS) or Data Protection (DP) or both. When enabled, Data Security disables reading the programmed contents of a device (the man.id and signature remain readable).
Page 38: Eztag With Workstations
XC95108 XC95216 EZTag software support the following capabilities. EZTag allows you to download a design to the EPLD on the target system. EZTag can verify EPLD conﬁguration by comparing it to the original JEDEC programming ﬁle after conﬁguring an EPLD.
Page 39: Design.jed
XC9500 devices. eztag.pro The eztag.pro ﬁle contains the default values for all EZTag options: part, design, baud, and port. These option values are updated at the end of every EZTag session. For EZTag to recognize an xchecker.pro ﬁle, it must be located in the same directory in which you started the...
Page 40: Verifying
When you do not specify any options, the EZTag software selects the port where the cable is connected and sets the baud rate to the maximum allowed by the platform. You can modify the communication port and baud rate by changing the appropriate settings in the xchecker.pro ﬁle.
Page 41: Command-Line Options
To execute a readback after the device has been in operation, use the interactive commands, as follows: eztag This command invokes the interactive mode, and the EZTAG ? prompt appears. part part_type:design_name The part commands identiﬁes the number the number, type, name and order of devices in the boundary-scan chain.
Page 42: Batch Batch Mode Operation
Abbreviation The Batch option executes commands in batch mode. The bat_file must have a ".cmd" extension and contain valid EZTag commands, including interactive commands. You can add comments to files by using the # symbol, either on the command line or on a new line.
Page 43: Verify Download And Readback
Abbreviation The Verify Download and Readback option executes a download and readback of the current EPLD design for veriﬁcation. EZTag reads the conﬁguration from the EPLD and compares it to the original bitstream. If you do not specify this option, readback is not executed after conﬁguration.
Page 44: Examples
EZTag with Workstations The Batch command executes commands in a batch mode. The bat_file must have a “.cmd” extension and contain valid EZTag commands. Use the pound sign, "#" to precede comment lines in the batch file. Examples The following examples show two methods of using the Batch command from the EZTag prompt: batch bat_file.
Page 45: Erase
The part_name must have been speciﬁed with the part command. Exit — Terminate Session Syntax exit Abbreviation The Exit command terminates the current EZTag session, asks you whether to save current program options in the xchecker.pro ﬁle, and returns you to the system shell. Functest Syntax functest part_name [-j ﬁle_name]...
Page 46: Log - Send Screen Display To File
EZTag with Workstations Log — Send Screen Display to File Syntax log –out file_name string Abbreviation The Log command sends the screen output to the file_name ﬁle. Use this command to capture the output of a Readback or a Show command.
Page 47: Port - Specify Download/Readback Port
EZTag with Workstations Abbreviation The partinfo command returns the manufacturer’s identiﬁcation (id), the user signature (-signature) or the device checksum (-checksum) for a particular part_name. Any or all of the three switches may be speciﬁed in a single command. The part_name must have been speciﬁed in the part command.
Page 48: Quit - Terminate Session
The device cannot be erased or re- programmed. Quit — Terminate Session Syntax quit Abbreviation The Quit command terminates the current EZTag session and asks you whether to save current program options in the xchecker.pro ﬁle. Reset — Reset Target LCA/Cable Syntax reset [–cable] Abbreviation The Reset command resets the boundary-scan TAP state machines or the XChecker cable.
Page 49: Settings - Display Settings
Sys —Temporarily Exit to Operating System Syntax Abbreviation none The Sys command allows you to temporarily exit from EZTag to the operating system prompt. Enter exit to return to EZTag. Verify — Verify Target EPLD Bitstream Syntax verify part_name [-j ﬁle_name] Abbreviation This command reads back the conﬁguration registers of the speciﬁed...
Page 50: Troubleshooting Guide
V Communication This section describes several issues that involve the integrity of the bitstream that EZTag transmits to the target EPLDs, and the correct connection of the boundary-scan chain. Improper Connections This section involves assigning conﬁguration pins to invalid signals or voltage levels.
Page 51: Improper Connections
+5 V and gnd to ground. For workstations, you must have read and write permissions to the port to which you connect the XChecker cable. EZTag might issue a message stating that the cable is not connected to port ttyx. When you...
Page 52 EZTag with Workstations 3. Turn on power to the target system. Warning: As with any CMOS device, the input/output pins of the internal FPGA should always be at a lower or equal potential than the rail voltage to avoid internal damage.
Page 53: Appendix A Error Messages
Appendix A Error Messages Introduction This section describes the error messages that EZTag may generate. Following each error message, there is a suggested workaround. Error Messages Error 001: Command file bat file.cmd is not found. Make sure that the command ﬁle you speciﬁed is in the current directory or the environment search path.
Page 54 PC (the XACT directory in the PC is equivalent to the “Installation Directory” on the workstations). Also make sure that eztag.hlp is in the directory XACT\MSG. If you cannot ﬁnd eztag.hlp in the XACT\MSG directory, you must reinstall the XChecker software.
Page 55 Refer to the XChecker Hardware section in Chapter 3 for help. Error 104: Invalid baud specified. Refer to the XChecker Hardware section in Chapter 3 for help. Error 105: Cable is not reset. Cycle power to the cable. Use the Reset command with the –c option. EZTag User Guide...
Page 56 The cable draws power from an external source, not from the host computer. Error 110: Communication time-out. EZTag has not received an expected signal; for example, a system trigger to initiate readback or data coming from readback. Make sure that the selected options for trigger and readback are what you intended.
Page 57 Error 131: Missing baud rate. Current baud rate is baud rate. See the Interactive Mode Commands section in Chapter 3 for correct command usage. Error 134: Cannot communicate with port port name. Check this manual for supported ports. See the Port command. EZTag User Guide...
Page 58 The speciﬁed device instance could not be veriﬁed. Check if data security is enabled as this disables the readback functionality. If this is not the case, check for the integrity of the cable connections. If error persists you may have a bad part and Xilinx customer service Xilinx Development System...
Page 59 If this is not the case, check for the integrity of the cable connections. If error persists you may have a bad part and Xilinx customer service should be contacted. error 1011: Verification failed at address value of instance string.
Page 60 If this is not the case, check for the integrity of the cable connections. If error persists you may have a bad part and Xilinx customer service should be contacted. Xilinx Development System...
Page 61 If this is not the case, check for the integrity of the cable connections. If error persists you may have a bad part and Xilinx customer service should be contacted. Error 1030: Unable to program data protect bit at address string on device string.
Page 62 This is the warning message issued when data security is enabled. It is displayed with each operation addressing this device. Error 1039: The device string is not a Xilinx part (IDCODE: string ) Error 1040: The device string is not a XC9500 part (IDCODE: string ) Please verify the specification of the order of the parts in the boundary-scan chain.
Page 63 If this is not the case, check for the integrity of the cable connections. If error persists you may have a bad part and Xilinx customer service should be contacted. Error 1047: Xchecker re-configuration file for boundary-scan TAP driver was not completed. Check XACT path setting, cable connections and version of file named ‘xckjtag.sys’.
Page 64 IEEE 1149.1 bypass instruction register INTEST ISPEN checksum JEDEC data protection data registers data security manufacturer’s ID data transfer modifications erase programming EXTEST readback FastFLASH feedback FERASE SAMPLE/PRELOAD flying lead connectors 2-10 security FPGM signature functional test FVFY EZTag User Guide...
Page 65 4-12 connecting to target system verifying configuration connecting control signals to VCC and ground 4-14 downloading files used hardware improper connections 4-14 invoking options command line displaying help executing batch file specifying part type specifying port names Xilinx Development System...

Xilinx EZTag User Manual

Chapter 1 Introduction

Chapter 2 Eztag Download Cable Options

Chapter 3 In-System Tutorial for Pcs Introduction

Chapter 4 Eztag with Workstations

Appendix A Error Messages

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Xilinx EZTag

Summary of Contents for Xilinx EZTag

Table of Contents