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EZTag with Workstations
3. Turn on power to the target system.
Warning: As with any CMOS device, the input/output pins of the
internal FPGA should always be at a lower or equal potential than
the rail voltage to avoid internal damage.
Make sure V
rises to a stable level within 10ms. Stable V
should
CC
CC
be between 4.75 V and 5.25 V.
In the event of power glitches, use the interactive Reset command
with the –c option (Cable option) to reconfigure the XChecker
internal FPGA and use the interactive program command to
reconfigure the target EPLD.
EZTag User Guide
4-15
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