Jtag Tap Controller - Xilinx EZTag User Manual

Introduction
is fed by TDI for a specific operation. TDI has an internal pull-up
resistor on it to provide a logic 1 to the system if the pin is not driven.
TDI is sampled into the JTAG registers on the rising edge of TCK.
TDO - this pin is the serial data output for all JTAG instruction and
data registers. The state of the TAP controller as well as the particular
instruction held in the instruction register determines which register
feeds TDO for a specific operation. Only one register (instruction or
data) is allowed to be the active connection between TDI and TDO for
any given operation. TDO changes state on the falling edge of TCK
and is only active during the shifting of data through the device. This
pin is three-stated at all other times.
Figure 1-1 JTAG Architecture

JTAG TAP Controller

The JTAG TAP Controller is a 16-state finite state machine, that
controls the scanning of data into the various registers of the JTAG
architecture. A state diagram of the TAP controller is shown in Figure
EZTag User Guide 1-3