Fujitsu F2MC-8L MB89620 Series Hardware Manual page 342

Register bank pointer (RP) ........................................................................................................................... 40
Reserved bit (RESV1) ................................................................................................................................ 252
S
Serial 1 data register (SDR1) ..................................................................................................................... 206
Serial 1 mode register (SMR1) ................................................................................................................... 204
Serial 2 data register (SDR2) ..................................................................................................................... 212
Serial 2 mode register (SMR2) ................................................................................................................... 210
Serial data output enable bit (SOE) .................................................................................................... 204, 210
Serial I/O transfer start bit (SST) ........................................................................................................ 204, 210
Shift clock output enable bit (SCKE) .................................................................................................. 204, 210
Shift clock selection bit (CKS0) .......................................................................................................... 204, 210
Shift clock selection bit (CKS1) .......................................................................................................... 204, 210
Sleep bit (SLP) .............................................................................................................................................. 70
Software reset bit (RST) ............................................................................................................................... 70
Stack pointer (SP) ......................................................................................................................................... 36
Standby control register (STBC).................................................................................................................... 70
Stop bit (STP) ................................................................................................................................................ 70
T
Temporary accumulator (T) .......................................................................................................................... 36
Timebase timer control register (TBTC) ..................................................................................................... 120
Timebase timer initialization bit (TBR) ........................................................................................................ 120
Timer output bit (TO) .................................................................................................................................. 166
Transfer direction selection bit (BDS) ................................................................................................. 204, 210
U
→ 00
Underflow (01
H
W
Watchdog timer control register (WDTC) ................................................................................................... 132
Watchdog timer control bit (WTE0) ............................................................................................................. 132
Watchdog timer control bit (WTE1) ............................................................................................................. 132
Watchdog timer control bit (WTE2) ............................................................................................................. 132
Watchdog timer control bit (WTE3) ............................................................................................................. 132
Z
Zero flag (Z) .................................................................................................................................................. 38
320
Register Index
) interrupt request flag bit (UF) ............................................................................... 164
H
MB89620 series