Figure B.1H Vector Addressing; Figure B.1I Relative Addressing; Figure B.1J Inherent Addressing - Fujitsu F2MC-8L MB89620 Series Hardware Manual

l Vector addressing
Indicated by "vct" in the instruction list. Used to branch to a subroutine address stored in the
vector table. For vector addressing, the "vct" data is contained in the operation code. Table B.1
lists the correspondence between "vct" and the resulting address.
Table B.1 Vector Table Addresses corresponding to "vct"
#vct Vector table address (branch destination upper address : lower address)
0
1
2
3
4
5
6
7
Figure B.1h shows an example.
l Relative addressing
Indicated by "rel" in the instruction list. Used to branch to a destination in the area 128 bytes
above or below the program counter (PC). Relative addressing adds the sign-extended contents
of the first operand to the PC and stores the result in the PC. Figure B.1i shows an example.
This example branches to the address containing the BNE operation code and therefore results
in an endless loop.
Inherent addressing
l
Inherent addressing is used for instructions in the instruction list that do not have operands and
for which the operation code determines the operation. The operation of inherent addressing
depends on the instruction. Figure B.1j shows an example.
276
APPENDIX
FFC0
FFC2
FFC4
FFC6
FFC8
FFCA
FFCC
FFCE
CALLV #5
(Conversion)

Figure B.1h Vector Addressing

BNE F EH
+
9ABC
H
Old PC

Figure B.1i Relative Addressing

NOP
+
9ABC
H
Old PC

Figure B.1j Inherent Addressing

:FFC1
H H
:FFC3
H H
:FFC5
H H
:FFC7
H H
:FFC9
H H
:FFCB
H H
:FFCD
H H
:FFCF
H H
FFCA FE
H H
FFCB DC
H H
9ABC + FFFE
H H
FEDC
H
PC
9ABA
H
New PC
9ABD
H
New PC
MB89620 series