Figure 10.7C 8-Bit Serial Input Operation - Fujitsu F2MC-8L MB89620 Series Hardware Manual

Figure 10.7c shows the 8-bit serial input operation.
For MSB first
SDR
n Operation at Completion of Serial Input
The 8-bit serial I/O sets the interrupt request flag bit (SMR: SIOF = "1") and clears the serial I/O
transfer start bit (SMR: SST = "0") on the rising edge of the shift clock after the serial data of the
eighth bit is input or output.
MB89620 series
Bit 7 Bit 6 Bit 5
#7 #6 #5
Serial
#7
input data
Shift clock
0
SIOF bit
SST bit

Figure 10.7c 8-bit Serial Input Operation

CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
Bit 4 Bit 3 Bit 2 Bit 1
#4 #3 #2
#6 #5 #4 #3
1 2 3 4
Automatically cleared when transfer completes.
Bit 0
SI pin
#1 #0
#2 #1 #0
Cleared
5 6 7 by program.
Interrupt request
10
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