Fujitsu F2MC-8L MB89620 Series Hardware Manual page 143

4
5. Timebase Timer Interrupt
The timebase timer can generate an interrupt request when an overflow occurs on the
specified bit of the timebase counter (for the interval timer function).
n Interrupts for Interval Timer Function
The counter counts-up on the internal count clock. When an overflow occurs on the selected
interval timer bit, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1". At this time,
an interrupt request (IRQA) to the CPU is generated if the interrupt request enable bit is enabled
(TBTC: TBIE="1"). Write "0" to the TBOF bit in the interrupt processing routine to clear the
interrupt request. The TBOF bit is set when the specified counter bit overflows, regardless of
the TBIE bit value.
Check: When enabling an interrupt request output (TBIE = "1") after wake-up from a reset, always clear
Notes: • An interrupt request is generated immediately if the TBOF bit is "1" when the TBIE bit is changed
n Stop Mode and Timebase Timer Interrupt
If the interval time is set shorter than the oscillation stabilization delay time, an interval interrupt
request from the timebase timer (TBTC: TBOF = "1") is generated at the time when the CPU
wakes up from stop mode by an external interrupt. In this case, disable the timebase timer
interrupt (TBTC: TBIE = "0") when changing to stop mode.
n Register and Vector Table for Timebase Timer Interrupt
Table 5.4 Register and Vector Table for Timebase Timer Interrupt
Interrupt
IRQA
Reference: See Section 3.4.2, "Interrupt Processing" for details on the interrupt operation.
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CHAPTER 5 TIMEBASE TIMER
the TBOF bit (TBOF = "0") at the same time.
from disabled to enabled ("0" → "1").
• The TBOF bit is not set if the counter is cleared (TBTC: TBR = "0") at the same time as an
overflow on the specified bit occurs.
Interrupt level setting register
Register
ILR3 (007E )
H
Setting bits
LA1 (Bit 5) LA0 (Bit 4)
Vector table address
Upper Lower
FFE6 FFE7
H H
MB89620 series