Fujitsu F2MC-8L MB89620 Series Hardware Manual page 128

4.5 Port 4
4.5.2 Operation of Port 4
This section describes the operations of the port 4.
n Operation of Port 4
l Operation as an output port
• Writing data to the PDR4 register stores the data in the output latch. When the output latch
value is "0," the output transistor turns "ON" and an "L" level is output from the pin. When the
output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance
state. If a pull-up is set to the output pin, the pin goes to the pull-up state when the output
latch value is "1".
• Reading the PDR4 register returns the pin value ("0" or "1", the same data as the output
latch).
Note: As the bit manipulation instructions (SETB and CLRB) read the output latch data rather than the pin
level, the instructions do not change the output latch values for bits other than the bit being set or
cleared.
Operation as an input port
l
• Setting the corresponding PDR4 register bit to "1" turns the output transistor "OFF" and sets
the pin to the high-impedance state.
• Reading the PDR4 register returns the pin value ("0" or "1").
Operation as a peripheral output
l
Set the output enable bit of the peripheral to use a pin as a peripheral output. As the pin value
can be read even if the peripheral output is enabled, the peripheral output value can be read.
The PDR4 register value has no effect on the peripheral output enable.
Operation as a peripheral input
l
The pin value is continuously input for ports that also serves as a pin with a peripheral input,
regardless of the PDR4 register setting value and of whether or not the peripheral is using the input
pin. When the peripheral is using the external signal, set the PDR4 register bit to "1" to turn the
output transistor "OFF".
Operation at reset
l
Resetting the CPU initializes the PDR4 register values to "1". This turns "OFF" the output
transistor for all pins (all pins become input ports) and sets the pins to the high-impedance state.
Operation in stop mode
l
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if
the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop mode.
Table 4.5.2 lists the port 4 pin states.
Table 4.5.2 Port 4 Pin State
Pin name
P40 to P47/SI2
SPL : Pin state specification bit in the standby control register (STBC)
Hi-z : High impedance
Note: Pins with a pull-up resistor (optional) go to the "H" level (pull-up state) rather than to the high-impedance
state when the output transistor is turned "OFF".
MB89620 series
Normal operation
Sleep mode
Stop mode (SPL=0)
General-purpose I/O ports/
peripheral I/O
Stop mode
(SPL=1)
Hi-z
CHAPTER 4 I/O PORTS
Reset
Hi-z
107