8-Bit Serial I/O Interrupts - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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10.

8-bit Serial I/O Interrupts

The 8-bit serial I/O can generate interrupt requests after completion of the serial input
and output of the 8-bit data.
Serial I/O-1 generates the IRQ7 as an interrupt request and serial I/O-2 generates the
IRQ8 as an interrupt request.
n Interrupt for Serial I/O Operation
The 8-bit serial I/O performs the serial input operation and serial output operation at the same
time. When the serial transfer starts, the data in the serial data register (SDR) is input and
output one bit at a time, synchronized with the cycle of the selected shift clock. The interrupt
request flag bit (SMR: SIOF) is set to "1" on the rising edge of the shift clock of the eighth bit.
At this time, an interrupt request (IRQ7 for serial I/O-1 and IRQ8 for serial I/O-2) to the CPU is
generated if the interrupt request enable bit is enabled (SMR: SIOE = "1").
Write "0" to the SIOF bit in the interrupt processing routine to clear the interrupt request. The
SIOF bit is set after completing 8-bit serial output, regardless of the SIOE bit value.
Note: The interrupt request flag bit is not set (SMR: SIOF = "1") if serial transfer is stopped (SMR: SST =
"0") at the same time as serial data transfer completes for the serial I/O operation. An interrupt
request is generated immediately if the SIOF bit is "1" when the SIOE bit is changed from disabled to
enabled ("0" → "1").
n Register and Vector Table for 8-bit Serial I/O Interrupts
Table 10.5 Register and Vector Table for 8-bit Serial I/O Interrupts
IRQ7 (8-bit serial I/O-1)
IRQ8 (8-bit serial I/O-2)
Reference: See Section 3.4.2, "Interrupt Processing" for details on the interrupts operation.
MB89620 series
Interrupt
Register
ILR2 (007D
ILR3 (007E
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
Interrupt level setting register
Setting bits
) L71 (Bit 7) L70 (Bit 6)
H
) L81 (Bit 1) L80 (Bit 0)
H
10
Vector table address
Upper Lower
FFEC FFED
H H
FFEA FFEB
H H
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