Fujitsu F2MC-8L MB89620 Series Hardware Manual page 151

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6. Overview of Watchdog Timer
The watchdog timer is a 1-bit counter that uses the timebase timer output as its count
clock. The watchdog timer resets the CPU if not cleared within a fixed time after
activation.
n Watchdog Timer Function
The watchdog timer is a counter provided to guard against program runaway. Once activated,
the counter must be repeatedly cleared within a fixed time interval. If the program becomes
trapped in an endless loop or similar and does not clear the counter within the fixed time, the
watchdog timer generates a four-instruction cycle watchdog reset to the CPU.
Table 6.1 lists the watchdog timer interval times. If not cleared, the watchdog timer generates a
watchdog reset at a time between the minimum and maximum times listed. Clear the counter
within the minimum time given in the table.
Table 6.1 Watchdog Timer Interval Time (for a 10 MHz source oscillation)
*: Divide-by-two source oscillation (F
Reference: See Section 6.4, "Operation of Watchdog Timer" for the details on the minimum and maximum
Check: The watchdog timer counter is cleared whenever the timebase timer is cleared (TBTC: TBR = "0").
Note: The watchdog timer counter is cleared whenever the device changes to sleep or stop mode or
enters the hold state. Operation halts until the device returns to normal operation (RUN state).
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CHAPTER 6 WATCHDOG TIMER
Count clock (for a 10-MHz main clock oscillation)
Minimum time
Maximum time
C
time of the watchdog timer interval times.
The watchdog timer does not function as intended if the timebase timer is repeatedly cleared
within the watchdog timer interval time.
Approx. 209.7 ms
Approx. 419.4 ms
) × maximum timebase timer count value (2
*
20 )
MB89620 series