Figure 10.9 Idle State Of Shift Clock; Notes On Using 8-Bit Serial I/O - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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10.

Notes on Using 8-bit Serial I/O

This section lists points to note when using the 8-bit serial I/O.
n Notes on Using 8-bit Serial I/O
l Error on starting serial transfer
As activating the serial transfer by software (SMR: SST = "1") is not synchronized with the
falling edge (output) or rising edge (input) of the shift clock, there is a delay of up to one cycle of
the selected shift clock before the first serial data I/O occurs.
Malfunction due to noise
l
In serial data transfer, malfunction of the serial I/O may occur if unwanted pulses (pulses
exceeding the hysteresis width) occur on the shift clock due to external noise.
Notes on setting by program
l
• Write to the serial mode register (SMR) and serial data register (SDR) when serial I/O is
stopped (SMR: SST = "0").
• Do not modify other SMR register bits when starting/enabling serial I/O transfer (SMR: SST =
"1").
• When using an external shift clock and when serial data output is enabled (SMR: SOE = "1"),
the output level on the SO pin when the external shift clock is input is the most significant bit
(when MSB first is selected) or least significant bit (when LSB first is selected). This applies
even if serial transfer is stopped (SMR: SST = "0").
• The interrupt request flag bit (SMR: SIOF) is not set if serial I/O transfer is stopped (SMR:
SST = "0") at the same time as serial data transfer completes.
• Interrupt processing cannot return if the SIOF bit is "1" and the interrupt request enable bit is
enabled (SIOE = "1"). Always clear the SIOF bit.
Transfer speed of serial I/O-2
l
The serial data output pin (SO2) for serial I/O-2 is an N-ch open-drain output and is not suitable
for high-speed transfer. Care is required when using serial I/O-2 with a high-speed shift clock.
Idle state of shift clock
l
Hold the external shift clock at the "H" level during the delay time between transfers of 8-bit data
(idle state). When set as the shift clock output (SMR2: SCKE = "1"), the internal shift clock
(SMR2: CKS1, CKS0 = other than "11
Figure 10.9 shows the idle state of the shift clock.
External shift
clock
220
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
") outputs an "H" level during the idle state.
B
Idle state 8-bit data transfer

Figure 10.9 Idle State of Shift Clock

8-bit data transfer
Idle state
Idle state
MB89620 series