Register Details: Watchdog Timer - Analog Devices ADuCM310 Hardware Reference Manual

UG-549

REGISTER DETAILS: WATCHDOG TIMER

Load Value Register
Address: 0x40002580, Reset: 0x1000, Name: T3LD
Table 248. Bit Descriptions for T3LD
Bits Bit Name
[15:0] LOAD
Current Count Value Register
Address: 0x40002584, Reset: 0x1000, Name: T3VAL
Table 249. Bit Descriptions for T3VAL
Bits Bit Name
[15:0] CCOUNT
Control Register
Address: 0x40002588, Reset: 0x00E9, Name: T3CON
Table 250. Bit Descriptions for T3CON
Bits Bit Name
[15:7] RESERVED
6 MOD
5 ENABLE
4 RESERVED
[3:2] PRE
1 IRQ
0 PMD
Description
Load value
Description
Current count value
Description
Reserved.
Timer mode. Note that in free running mode, it wraps around at 0x1000.
0: FREERUN. Cleared by user to operate in free running mode.
1: PERIODIC. Set by user to operate in periodic mode (default).
Timer enable.
0: DIS. Cleared by user to disable the timer.
1: EN. Set by user to enable the timer (default).
Reserved.
Prescaler.
00: DIV1. Source Clock/1.
01: DIV16. Source Clock/16.
10: DIV256. Source Clock/256 (default).
11: DIV4096. Source Clock/4096
Timer interrupt.
0: DIS. Cleared by user to generate a reset on a time out (default).
1: EN. Set by user to generate an interrupt when the timer times out. This
feature is provided for debug purposes and is only available in active mode.
Power mode disable. PMD controls the behavior of the watchdog when in
hibernate mode. If the application requires prolonged periods of time spent
in hibernate mode and it is not desirable to periodically wake up to service the
watchdog timer, the counter within the watchdog timer can be suspended
when entering the hibernate power mode. Regardless of how the PMD bit
is set, it is recommended that the watchdog timer be cleared before
entering hibernate mode.
0: DIS. The watchdog timer continues its count down while in hibernate mode.
1: EN. When hibernate mode is entered, the watchdog counter suspends
its countdown. As hibernate mode is exited, the countdown resumes from
its current count value (the count is not reset).
Rev. C | Page 170 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x1000 RW
Reset Access
0x1000 R
Reset Access
0x1 R
0x1 RW
0x1 RW
0x0 R
0x2 RW
0x0 RW
0x1 RW