Analog Devices ADuCM310 Hardware Reference Manual page 118

UG-549
First Master Address Byte Register
Address: 0x40003018, Reset: 0x0000, Name: I2CADR0
Table 159. Bit Descriptions for I2CADR0
Bits Bit Name
[15:8] RESERVED
[7:0] ADR0
Second Master Address Byte Register
Address: 0x4000301C, Reset: 0x0000, Name: I2CADR1
Table 160. Bit Descriptions for I2CADR1
Bits Bit Name
[15:8] RESERVED
[7:0] ADR1
Serial Clock Period Divisor Register
Address: 0x40003024, Reset: 0x1F1F, Name: I2CDIV
Table 161. Bit Descriptions for I2CDIV
Bits Bit Name
[15:8] HIGH
[7:0] LOW
Description
Reserved.
Address Byte 0. If a 7-bit address is required, Bit 7 to Bit 1 of ADR0 are
programmed with the address, and Bit 0 of ADR0 is programmed with the
direction (0 = write, 1 = read). If a 10-bit address is required, Bit 7 to Bit 3 of
ADR0 are programmed with 11110, Bit 2 to Bit 1 of ADR0 are programmed
with the 2 MSBs of the address, and Bit 0 of ADR0 is programmed to 0.
Description
Reserved.
Address Byte 1. This register is only required when addressing a slave with
a 10-bit address. Bit 7 to Bit 0 of ADR1 are programmed with the lower
8 bits of the address.
Description
Serial clock high time. This register controls the clock high time. The timer
is driven by the core clock (UCLK). Use the following equation to derive the
required high time:
HIGH = (REQD_HIGH_TIME/UCLK_PERIOD) − 2
For example, to generate a 400 kHz SCL with a low time of 1300 ns and a
high time of 1200 ns, with a core clock frequency of 50 MHz:
LOWTIME = 1300 ns/20 ns − 1 = 0x40 (64 decimal)
HIGH = 1200 ns/20 ns − 2 = 0x3A (58 decimal)
This register is reset to 0x1F, which gives an SCL high time of 33 UCLK ticks.
t is also determined by the high time.
HD:STA
t = (HIGH − 1) × UCLK_PERIOD
HD:STA
Because t must be 600 ns, with UCLK = 50 MHz, the minimum value
HD:STA
for HIGH is 31. This gives an SCL high time of 660 ns.
Serial clock low time. This register controls the clock low time. The timer is
driven by the core clock (UCLK). Use the following equation to derive the
required low time.
LOW = (REQD_LOW_TIME/UCLK_PERIOD) − 1
This register is reset to 0x1F, which gives an SCL low time of 32 UCLK ticks.
Rev. C | Page 118 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 R
0x0 RW
Reset Access
0x1F RW
0x1F RW